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\begin{document}

\title{AN ADIABATIC LOGIC IMPLEMENTATION OF A REVERSIBLE CELLULAR AUTOMATON}
\author{Michael P. Frank \and Nicole Love}
\affiliation{
Artificial Intelligence Laboratory\\
Massachusetts Institute of Technology \\
Cambridge, MA 02139\\
}
\maketitle 

\begin{abstract}
Adiabatic circuit techniques have lately been a topic of interest in
the low-power design community, but nobody has yet designed a complete
computer using only adiabatic logic.  We have (almost) completed the
circuit design and layout of a simple fully-adiabatic processing
element (PE) that nevertheless comprises a general-purpose parallel
processor when tiled in large arrays.  This PE implements the local
update rule for Margolus's Billiard Ball Model Cellular Automaton
\cite{m}, a reversible universal model of computation.  The
PE is implemented using Younis and Knight's SCRL logic family
\cite{yk}.  Our cell contains just 292 transistors and tiles
on a $131\times 117$ $\mu m^2$ grid in the HP14 process.
Hand-calculations indicate that our adiabatic circuit can operate with
up to about 1000 times the energy efficiency of the equivalent
standard CMOS circuit.
\end{abstract}

\section{Introduction}

Microscopic physical dynamics is invertible, which suggests that an
optimal computation technology using this dynamics would be reversible
as well \cite{m}.  Any operation that is not reversible is required by
thermodynamics to dissipate energy $k_BT\ln 2$, where $k_B$ is
Boltzmann's constant and $T$ is the temperature in K, per bit of
information discarded.  Current computers dissipate far more energy
than this, namely ${1\over 2}CV^2$, where $C$ is node capacitance and
$V$ is voltage swing, whenever they change the voltage of an internal
node.

However, recent developments in the field of adiabatic circuits have
shown that this $CV^2$ energy per operation is not really necessary.
If circuit nodes are charged and discharged gradually and reversibly,
they can operate {\em adiabatically} (a term from thermodynamics
meaning ``without heat flow'').

Despite the interest in adibatic computation, nobody has yet carried
through the exercise of designing a complete computer based on totally
reversible adiabatic technology.  Such a design would demonstrate the
physical realizability of universal reversible computation and give us
practice analyzing and programming such computers, which could be
useful if we ever do approach the scale where reversibility is
required for efficiency, by the laws of physics.  So for our project
we decided to design a very simple adiabatic computer, using a
fully-adiabatic circuit technology called SCRL (Split-level Charge
Recovery Logic) developed earlier at our lab.  Later, the design will
be fabricated and tested by the MIT Reversible Computing project, and
will serve as a benchmark test chip for evaluating SCRL with different
adibatic rail driver technologies.

To make the project feasible, we chose the simplest parallel universal
computer model we knew about, namely that of Margolus's Billiard Ball
Model Cellular Automaton (BBMCA) \cite{m}.  It is not exactly the most
convenient computer to program, but it is simple, universal,
reversible, and scalable.

In the following sections, we note a few facts about SCRL and BBMCA,
describe our circuit design and layout, and provide hand-analysis
indicating the power savings achieved by our circuit.

\section{SCRL}

SCRL \cite{yk,y} has several advantages over its predecessors in
adiabatic logic.  The main one is that SCRL can be pipelined, allowing
for continuously-running, sequential adiabatic circuits.  This
pipelining requires that each gate be paired with another gate to
compute the reverse function.

Normal SCRL stages cannot compute non-inverting logic functions, but
it is actually possible to compute non-inverting functions by
providing an extra pair of ``fast'' rails that split before the main
rails do, and re-combine after the main ones.  (See \cite{yk,y}.)
These rails can be used to drive an extra level of logic (such as
inverters) to feed the inputs of the main logicq.  In this way, a
single SCRL stage can compute any logic function.  We used this trick
to help make our circuits simpler.

SCRL, along with many other adiabatic circuit families, requires a
power supply that can generate many resonant, swinging supply rails
with low dissipation.  If the power supplies do not have enough
efficiency, that will limit our power savings.  The development of a
satisfactory power supply is an active research topic, but in this
paper we assume it's given.

\section{The BBMCA}

In the billiard-ball model of computation, signals are represented by
the presence or absence of billiard balls moving along predetermined
paths in a grid.  A logic gate is a point where two potential ball
trajectories interact.  Fixed walls bounce signals around.  Any
reversible sequential logic circuit can be implemented in this model.

The BBM cellular automaton simulates the billiard ball model by
representing balls and walls as 1s, and empty space as 0s in a grid.
The grid is subdivided into 2x2 blocks, in two different alignments of
subdivisions, which alternate between cycles, and are offset from each
other by 1 cell in each of the x and y directions.

On each cycle, the contents of each block in the array are modified
according a simple reversible transformation.  Figure \ref{fig:rules}
shows the BBMCA update rules.  The rules are applied independently of
block orientation.  All configurations other than those listed remain
constant.  Fixed features can be constructed out of several adjacent
bits that are all on.  Bits that are isolated move diagonally through
the array.

\begin{figure}
\centerline{\psfig{width=3in,rheight=.6in,file=BBMrules.epsi}}
\caption{BBMCA block update rules.}
\label{fig:rules}
\end{figure}

We implement the CA by placing an SCRL processor at the center of
every 2x2 block on each of the two alignments.  The processor takes
its inputs from block's four cells (which are really just wires coming
from the processors in the centers of the four overlapping blocks) and
produces its outputs in those same cells, but shifted to an alternate
bit-plane (another set of four wires going back out to the neighboring
processors).  The wires going off the edges of the array can be folded
back into the array to connect the two bit-planes, or fed out to
neighboring chips in a larger array.

\section{Circuit Design}

We decided to focus on so-called ``3-phase SCRL'' \cite{y} for
implementing our array because it is the simplest version of SCRL that
doesn't depend on dynamic charge storage, and we wanted to be able to
run the clocks arbitrarily slowly or stop them altogether without
worrying about losing our logic values, in order to make testing
easier.

One constraint of 3-phase SCRL is that all circular pipelines must be
a multiple of 3 stages long.  We chose 6 stages for the complete cycle
of interaction from a cell to its neighbors and back, with 3 stages in
each cell, and all cells identical.  The 2-cell loop could perhaps
have been accomplished in 3 stages, but it seemed that this would
require more fast rails, and two asymmetrically different types of
cells.

\subsection{Logic Minimization}

We spent a fair amount of time early in the project figuring out how
to implement the BBMCA update rule in 3 SCRL stages using a minimum
amount of logic.  Initial concepts had 600 transistors, but finally we
arrived at a 240-transistor design.  However, this did not allow array
initialization, so later we tacked extra logic onto the design which
increased the count to 292.  It's possible to get by with less, but we
haven't had time to re-minimize the logic since adding initialization.

The initial 240-transistor logic involved stages generating the
following signals.  The inputs to stage 1 are $A,B,C,D$.

\begin{itemize}
\item Stage 1. $\overline{A}$, $\overline{B}$, $\overline{C}$,
$\overline{D}$, $\overline{S} = \overline{(A+C)(B+D)}$.
\item Stage 2. $A$, $B$, $C$, $D$, $S$, $\overline{S}$,
$\overline{A_{out}} = \overline{SA+\overline{S}\overline{A}(C+BD)}$,
and similarly for $B_{out}$, $C_{out}$, $D_{out}$.
\item Stage 3. $A_{out}$, $B_{out}$, $C_{out}$, $D_{out}$.
\end{itemize}

In this logic, stage 1 is mainly a buffer, but also generates the $S$
signal which is used in stage 2.  Stage 2 does all the real work of
computing the update function, and stage 3 is another buffer.  The
reason stage 2 must produce S at its output is so that S will be
available for use by the reverse half of stage 2, to compute the
inverse update function.

The new logic is shown in the schematics section.

\subsection{Block Diagram}

Figure \ref{fig:cell2} shows a schematic block diagram of a single
processing element cell.  Note the three forward stages along the top,
and the three reverse stages along the bottom.  There is a mistake in
this diagram that was added when incorporating initialization
circuitry but we have not yet had time to correct it.  (The diagram
shows the reverse part of the first stage being identical to the
forward stage 3, and vice-versa, whereas this should not actually the
case, due to asymmetry in our initialization scheme.)  The $sh$ and
$\overline{sh}$ signals down the middle determine whether the array is
in initialization mode or computation mode.

Along the bottom are shown the 22 SCRL rails that go to each cell: six
swinging supply rails and their complements, two ``fast'' supply rails
and their complements for use in stage 2, and three pass transistor
control rails and their complements.  Not shown are the constant
$V_{dd}$ and GND rails, which go everywhere to set bulk voltage
levels, but carry no current (except for that due to diode leakage).

\begin{figure}
\centerline{\psfig{width=3in,rheight=1.4in,file=Cell2.eps}}
\caption{Block diagram of PE cell.}
\label{fig:cell2}
\end{figure}

\subsection{Schematics}

Below are the schematics for the logic in the forward stages.  The
reverse stages are very similar.  We have not yet had time to size the
transistors in our design so as to minimize power, but within each
gate, we have, for uniformity, sized its transistors so that the
worst-case transition times are the same as that of an inverter with a
minimum-width NFET and a twice-minimum-width PFET.  (The layout does
not yet reflect exactly this sizing in all cases.)

Figure \ref{fig:stage1} shows the logic in stage 1 which computes the
inverses of the inputs, together with the S (static) signal used in
stage 2.  Note that S is turned on when in $sh$ (shift) mode.  This
special case was added to support array initialization.

\begin{figure}
\centerline{\psfig{width=1.5in,file=Stage1.eps}\psfig{width=1.5in,file=Stage2_gate.eps}}
\caption{Stage 1 logic, $\overline{S}=\overline{sh + (A+C)(B+D)}$.
Gate for computing $\overline{A_{out}}$ in stage 2.}
\label{fig:stage1}
\end{figure}

The figure also shows the gate used for computing each second-stage
output.  Stage 2 includes four repititions of this gate, differing as
to which inputs are fed to the $A,B,C,D$ pins, plus 5 ``fast''
inverters for generating the $A,B,C,D,S$ signals from their inverses
using the $f\phi_2$ and $\overline{f\phi_2t}$ rails, plus one other
inverter for generating $\overline{S}$ on the stage 2 output.

Finally, figure \ref{fig:gate3} shows the gate that is repeated four
times (with different pin assignments) in stage 3.  This gate selects
either $A$ or the bit in the opposite corner of the block for passing
through to the output, depending on $sh$.  Thus if $sh$ is on, input
bits go to the opposite output bits, enabling the array as a whole to
act as one large shift register, which can be used to initialize the
array contents.

\begin{figure}
\centerline{\psfig{width=3.5in,rheight=1.9in,file=Stage3_gate.eps}}
\caption{Gate for computing
$A'=\overline{\overline{sh}\ \overline{A} + sh\ \overline{C}}$ in stage 3.}
\label{fig:gate3}
\end{figure}

\subsection{Layout}

Figure \ref{fig:layout} shows our current cell layout, with metal
layers 2 and 3 stripped off for clarity.  The inputs are on the left,
outputs on the right.  The forward stages run left to right across the
top, reverse stages right to left across the bottom.  The metal2 layer
is used for some local connections, but is primarily reserved for
horizontal channels across the cell for routing the 26 global signals
to all the cells in a row of the array; metal3 is used similarly in
vertical stripes to tie rows of cells together.

\begin{figure}
\centerline{\psfig{angle=-90,width=3in,rheight=2.9in,file=layout-m2.eps}}
\caption{Current cell layout.}
\label{fig:layout}
\end{figure}

The layout is highly symmetrical due to the fact that the BBMCA update
rule is self-reversing so that the reverse SCRL stages are identical
to the forward ones.  But actually the symmetry here is a mistake; we
broke the symmetry when we introduced array initialization circuitry
late in the design process.  This new circuitry should have gone into
just the third SCRL stage, but out of habit, we incorporated it
symmetrically into the first and third stages, which doesn't work.

Besides this, we are fairly proud of our layout job; transistors are
arranged along neat rows of diffusion to minimize junction area and
perimiter capacitances, wire routing is neat and orderly, and things
are generally packed as tightly as possible to minimize overall cell
area.  We perhaps spent too much time on layout, but are generally
pleased with the results.

\section{Hand-analysis}

Determining the energy/power dissipation for an adiabatic circuit
requires a massive amount of hand calculations.  Therefore we decided
to make several assumptions and approximations to simplify the hand
calculations.  Producing results which we believe are a first order
approximation of the power/energy dissipation.  The initial
assumptions consist of ignoring body effect and channel length
modulation.  Our hand calculations begin by determining the capacitive
loads on the output of each stage of the circuit.  The circuit
consists of three forward stages and three reverse stages, there are
two possible drivers for each load line, a forward stage gate or a
reverse stage gate.  The load line drives two stages the following
stage and the reverse stage.  For example, the capacitance on the load
line of Stage 1 consists of the drain capacitance of Stage 1 and Stage
2R and the gate capacitance of Stage 2 and Stage 1R.  Using the values
shown in Table~\ref{tbl:cap}, equation~\ref{eq:cdb}, and
equation~\ref{eq:cg} the worst-case capacitance of a load line was
determined, C$_L$.  The capacitance per signal was calculated to be
$\approx$170fF.

\begin{table}
\caption{Cadence Device Parameters}
\label{tbl:cap}

\begin{tabular}{|c|c|c|c|}
\hline
\multicolumn{2}{|c|}{NMOS} & \multicolumn{2}{c|}{PMOS} \\
\hline
Var & Value & Var & Value \\
\hline
$\phi_{0}$ & 1.1V & $\phi_{0}$ & 0.8993 \\
\hline
m$_j$ & 0.726 & m$_j$ & 0.4905 \\
\hline
m$_{jsw}$ & 0.2451 & m$_{jsw}$ & 0.2451 \\
\hline
C$_j$ & 4.67x10$^{-4}$ F/m$^2$ & C$_j$ & 8.76x10$^{-4}$ F/m$^2$ \\
\hline
C$_{jsw}$ & 3.20x10$^{-10}$ F/m & C$_{jsw}$ & 2.13x10$^{-10}$ F/m \\
\hline
t$_{ox}$ & 9nm & t$_{ox}$ & 9nm \\
\hline
$\mu_n$ & 978.1 cm$^2$/V$^2$-s & $\mu_p$ & 228.5 cm$^2$/V$^2$-s \\
\hline
C$_{ox}$ & 3.89x10$^{-15}$ F/$\mu$m$^2$ & C$_{ox}$ & 3.89x10$^{-15}$ F/$\mu$m$^2$ \\
\hline
{k'}$_n$ & 3.80x10$^{-4}$ A/V$^2$ & {k'}$_p$ & 8.889x10$^{-5}$ A/V$^2$ \\
\hline
\end{tabular}
\end{table}

\begin{eqnarray}
C_{db} & = & {K_{eq}}_j * C_j * AD_n + {K_{eq}}_{jsw} * C_{jsw} * PD_n \label{eq:cdb} \\
K_{eq} & = & \frac{-{{\phi}_0}^m\left[{\left({\phi}_0 - V_{high}\right)}^{1-m} - {\left({\phi}_0 - V_{low}\right)}^{1-m}\right]}{\left(V_{high} - V_{low}\right)\left(1 - m\right)} \\
C_g & = & C_{ox}WL \label{eq:cg}
\end{eqnarray}

C$_L$ is used to determine an estimate of the maximum current being
drawn from the rails. In an adiabatic circuit determining the
characteristics of the circuit during the transient is extremely
difficult because both the source and the drain are changing.  In
adiabatic circuits switching the rails slowly produces a smooth
transition because the capacitive load has enough time to charge up
with the rail.  With a slow changing rail the drain follows the source
with a small lag, this lag is V$_{DS}$ which will be constant during
most of the switching time.  We assume the rails are switching slow
enough to produce a fairly constant V$_{DS}$ which we label as
V$_{DSest}$.  We use a crude estimate of the current shown in
equation~\ref{eq:i} based on the voltage change at the output.  With
the assumption that the rail is changing slowly this approximation of
the current should be close to the average current during the
transient.  In calculating V$_{DSest}$ we also approximate V$_{GS}$ to
be it's value at the halfway mark of the transient, which seems to be
a fair approximation for a first order approximation.
Table~\ref{tbl:res} shows the results of calculating I$_{est}$ and
V$_{DSest}$ with varying rise/fall times.

\begin{eqnarray}
I_{est} & = & C_L\frac{\delta V_{out}}{t_r} \label{eq:i}\\
I_{est} & = & k'_p\frac{W}{L}\left[\left({\overline{V}}_{GS} - V_T\right)V_{DSest} - \frac{{V_{DS}}^2}{2} \right]\\
V_{DSest} & = & {\overline{V}}_{GS} - \sqrt{{\overline{V}_{GS}}^2 - 2\frac{I_{est}}{k_p}}
\end{eqnarray}

\begin{table}
\caption{Adiabatic E$_{dis}$ vs t$_{rf}$}
\label{tbl:res}

\begin{tabular}{|c|c|c|c|c|c|c|c|}
\hline
t$_{rf}$ & I$_{est}$ & V$_{DS}$	& E$_{sw}$/cyc & P$_{sw}$ & E$_{leak}$ \\
\hline
1ns & 280.5$\mu$A & 0.22V & 2.71pJ & 113$\mu$W & 9.5aJ\\
\hline
10ns & 28.0$\mu$A & 0.021V & 264fJ & 1.1$\mu$W & 95aJ\\
\hline
100ns & 2.80$\mu$A & 2mV & 26fJ & 10.8nW & 950aJ\\
\hline
1$\mu$s & 280nA & 207$\mu$V & 2.6fJ & 108pW & 9.5fJ\\
\hline
10$\mu$s & 28.0nA & 20$\mu$V & 260aJ & 1.08pW & 95fJ\\
\hline
100$\mu$s & 2.80nA & 2$\mu$V & 26aJ & 10.8fW & 950fJ\\
\hline
1ms & 0.280nA & 200nV & 2.6aJ & 0.108fW & 9.5pJ\\
\hline
\end{tabular}
\end{table}

The equation used for energy dissipation due to switching of the
adiabatic circuit was determined by intergrating the power=IV over the
rise/fall time of rails.  Using equation~\ref{eq:Esw} the energy per
signal per cycle was calculated and is shown in Table~\ref{tbl:res}.
The energy dissipated due to leakage was calculated using I$_{leak} =
10^{-11}$A as the leakage current through a transistor (Cadence device
characteristics).  From the table it is clear that the energy due to
switching is proportional to the inverse of t$_{rf}$ and the energy
due to the leakage is proportional to t$_{rf}$.  Therefore
equation~\ref{eq:prop} shows E$_{tot}$ with the proportionality
constants K$_{sw}$ and K$_{leak}$ referring to the switching and
leakage energy respectively.  Using this equation the optimum t$_{rf}$
can be found which minimizes the energy dissipated by the circuit.

\begin{eqnarray}
\left({E_{sw}}_{dis}/signal\right)/cycle & = & 2I_{est}V_{DSest}t_{rf} \label{eq:Esw} \\
E_{tot} & = & E_{sw} + E_{leak} \\
E_{tot} & = & \frac{K_{sw}}{t_{rf}} + K_{leak}t_{rf} \label{eq:prop}\\
{t_{rf}}_{opt} & = & 523ns \\
{t_{cycle}}_{opt} & = & 24t_{rf} = 12.5{\mu}s 
\end{eqnarray}

In comparison, implementing the same circuit using conventional CMOS
required 4 stages corresponding to the three stages and the fast stage
of the adiabatic circuit.  The energy dissipated by the CMOS circuit
is given by equation~\ref{eq:Etot}.  Where the first term is the
energy dissipated due to switching and the second due to short circuit
current.  Equation~\ref{eq:Etot} assumes worst-case switching activity
(i.e. $\alpha = 1$).  In conventional CMOS the reversible stages are
not needed therefore the load capacitance of the circuit will be
approximately half the capacitance of the adiabatic circuit.  The
total energy dissipated per cycle for the convntional CMOS circuit is
21.4pJ/cycle.  The propagation delay of the conventional CMOS circuit
using equation~\ref{eq:td} is 59.5ps/stage therefore the total
propagation delay for the four stages is 238ps.  The propagation delay
for the adiabatic circuit using the same equation is 260ps/edge and
there are 24 edges used to propagate through the three stages,
therefore the total propagation delay is 6240ps.  Table~\ref{tbl:comp}
is a summary of the comparison of the conventional CMOS vs. an
adiabatic version.  The conventional CMOS circuit has a propagation
delay which is more than 26 times less than the propagation delay of
the adiabatic circuit.  The energy savings of $\approx$ 2000!!! by the
adiabatic circuit over the conventional CMOS circuit is enormous.  The
worst-case energy dissipation for the adiabatic circuit is assuming
that the power supplies are switching instantaneously and therefore
the same equation used for energy dissipation due to switching can be
used as an approximation for the adiabatic circuit.  The worst-case
energy dissipation is 10.38pJ/cycle.

\begin{eqnarray}
E_{tot}/cycle & = & \frac{1}{2}C_L{V_{dd}}^2 + t_{rf}I_{peak}V_{dd} \label{eq:Etot} \\
t_d & = & \frac{C_L\left(V_2 - V_1\right)}{I_{av}} \label{eq:td}
\end{eqnarray}

\begin{table}
\caption{CMOS vs Adiabatic}
\label{tbl:comp}
\begin{tabular}{|c|c|c||c|}
\hline
Var & CMOS & Adi. & Adi./CMOS \\
\hline
E (pJ/cyc) & 21.4 & 9.9x10$^{-3}$ & 1/2164\\
\hline
prop. del.(ps) & 238 & 6240 & 26 \\
\hline
worst E (pJ/cyc) & 21.4 & 10.38 & .5 \\ 
\hline
\end{tabular}
\end{table}



\section{Conclusion}

We have created the world's first complete (though still slightly
buggy) circuit- and layout-level design for a fully adibatic and
reversible universal computer.  The architecture is parallel and
scalable to arbitrarily large arrays, assuming power supply inputs are
repeated periodically.  (Global timing skew is not an issue since all
data interconnections are local.)  We have thus provided the first
concrete example of a piece of hardware that can be programmed to
perform arbitrary computations using arbitrarily little energy per
operation (ignoring leakage).  Even when actual leakage factors are
taken into account, our circuit can still operate with less than one
thousandth of the energy per operation of a traditional circuit
implementing the same computation model.  Assuming adequate power
supplies can be built, our design and analysis illustrate the enormous
power benefits that can be gained by computing adibatically.

\begin{thebibliography}{10}

\bibitem{yk} Younis, S. G. and Knight, Jr., T. F.,  ``Asymptotically Zero Energy
Split-Level Charge Recovery Logic.''  International Workshop on Low
Power Design, pp. 177--182, 1994. {\url http://www.ai.mit.edu/people/tk/lowpower/low94.ps}

\bibitem{y} Younis, S. G., {\it Asymptotically Zero Energy Computing Using
Split-Level Charge Recovery Logic}, Ph.D. Thesis, MIT Artificial
Intelligence Laboratory, 1994.

\bibitem{m} Margolus, N. H., {\it Physics and Computation}, Ph.D. Thesis, MIT
Physics Department, 1987. 

%\bibitem{h} Hall, J. S., ``An Electroid Switching Model for Reversible Computer
%Architectures,'' {\it Proceedings of the Workshop on Physics and
%Computation}, pp. 237--247, 1992.
%
%\bibitem{l} Likharev, K. K., ``Classical and Quantum Limitations on
%Energy Consumption in Computation,'' {\it International Journal of
%Theoretical Physics}, {\bf 21}(3/4):311--326, 1982.

\end{thebibliography}
\end{document}


