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% circuits.tex - Analysis & Design of Adiabatic Circuits
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\chapter{Adiabatic circuits}
\label{ch:circuits}

\index{circuits!adiabatic|(textbf}

\def\draftid{$\ $Id: circuits.tex,v 1.3.2.10.2.5 1999/05/14 15:43:25 mpf Exp $\ $}

{\ed{This chapter is very long (~66 pp)...  Should I (a) break it up into
separate chapters, (b) eliminate some content, or (c) try to make the
existing content more concise?  Or some combination of these?
Sections~\ref{sec:mincmos} and~\ref{sec:scrlexp} would be good candidates
for moving out into their own chapters.}}

Part I of this thesis explored the general motivation for and properties of
reversible machines, without reference to any particular implementation
technology.  In Part II, beginning with this chapter, we address a variety
of engineering and implementation issues in reversible computing, showing
ways to actually design, build, and program reversible computers.

Virtually all computers today are built using semiconductor VLSI
(very-large scale integration) technology, in which, typically,
metal-oxide-semiconductor field-effect transistors (MOSFETs) are wired
together to form CMOS (complementary MOS) logic gates.

Unfortunately, the way these CMOS logic gates are currently designed, they
are operationally irreversible, and thus have fixed lower bounds on their
energy dissipation and entropy generation, which we will analyze in some
detail in {\S\ref{sec:mincmos}}.  These bounds have consequences for the
maximum cost-efficiency of computation using irreversible CMOS (hereafter
abbreviated ``iCMOS'') under various cost measures.

The irreversibility of traditional logic elements has led researchers to
ask whether transistor electronics could instead be configured in such a
way as to form reversible logic elements.  The answer is yes, there is a
class of reversible logic circuit styles called ``adiabatic'' circuits (a
somewhat misleading name, as we will explain in~\S\ref{sec:adia-rant}),
whose history we will review.  We will then describe in detail
{\emph{SCRL}} (split-level charge recovery logic), a particular variant of
adiabatic circuit technology that was developed a few years ago by members
of our research group
{\cite{Younis-Knight-93,Younis-Knight-94,Younis-94,Younis-Knight-95}}.
SCRL has several properties that make it particularly suitable for
achieving the asymptotic efficiency benefits that we discussed in
ch.~\ref{ch:scaling}.  It is capable of full reversibility.  It can be
built cheaply and easily using today's commercially available VLSI
fabrication processes.  And SCRL's energy dissipation roughly matches the
{\TRA} (time-proportionately reversible) model of chapter~\ref{ch:scaling}.

Next, we describe our SCRL-based design of {\FlatTop}, a simple adiabatic
circuit that we recently fabricated {\cite{Frank-etal-98a}}.  This circuit
can be viewed as the first ever universal reversible processor core,
capable, in principle, of fulfilling the scaling laws derived in the
previous chapter, and thereby computing asymptotically faster than any
irreversible technology in machines at a sufficiently large scale.
(However, in practice, the {\FlatTop} chip is really just a proof of concept.)

Unfortunately, with some additional analysis (not contained in this thesis)
we have found that the constant factors of present-day VLSI (very
large-scale integration) semiconductor technology imply that the cost level
at which reversible computing will actually dominate in speed is, in the
present technology generation, economically infeasible (roughly speaking,
in the range of billions of dollars).  In the following chapter, we will
review a variety of possible future device technologies for which, in
contrast, reversibility wins out for all but the tiniest of machines.
Then, chapter~\ref{ch:program} will review reversible programming issues.

\section{Maximizing the efficiency of iCMOS}
\label{sec:mincmos}

Before we describe SCRL, in this section we will establish a baseline for
comparison by roughly estimating the optimum performance of present and
future irreversible CMOS, under a variety of cost-efficiency measures.

The central motivation for adiabatic circuits is the avoidance of the $\sim
CV^2$ energy dissipation that (as we will see) is necessarily incurred by
ordinary irreversible logic circuits whenever they switch a signal from one
logic level to another.  In this section we briefly review traditional
irreversible CMOS logic, and the reasons for its energy dissipation, and
analyze in some detail the present and future minimum energy dissipation of
such circuits, based on the semiconductor industry's technology projections
for the next decade.  This analysis can serve as a baseline for comparison
when we wish to look at the capabilities of adiabatic circuits.

\subsection{Basic iCMOS review}
\label{sec:icmos}

A detailed description of irreversible CMOS technology can be found in any
standard, reasonably recent VLSI textbook, for example
{\cite{Hodges-Jackson-88,Weste-Eshraghian-93,Rabaey96}}.  Here, we only
briefly review the basics.

CMOS logic gates may appear in the simple {\defn{static}} form, or in
various {\defn{dynamic}} variations.  In this context, ``static'' and
``dynamic'' refer to whether the output of the logic gate is always tied to
a fixed voltage source, or is sometimes allowed to float freely.  The
underlying energy issues in the two circuit styles are basically similar,
so to ease our analysis, we will focus on the simplest static logic style.
The use of alternative styles of irreversible CMOS logic can improve energy
efficiency beyond that of ordinary static CMOS by, at most, only a small
constant factor.

Figure~\ref{fig:inv} shows a static CMOS inverter, consisting of two
MOSFETs, one n-type and one p-type.  (The n and p refer to whether the
primary charge carriers in the device are negatively charged electrons or
positively charged ``holes.'')  The {\pFET} connects the output to a high
voltage when the input is low, and the {\nFET} connects the output to a low
voltage when the input is high.

\begin{figure}
\centerline{%
(a)\psfig{width=2.7in,file=inv.epsi}%
(b)\psfig{width=2.7in,file=cmos1.epsi}}
\caption[Ordinary CMOS inverter]{(a) An ordinary CMOS inverter, consisting of
an {\nFET} (bottom) and a {\pFET} (top).  Given an input logic value $A$,
the inverter computes its inverse $\bar{A}$.  With more complex networks of
{\pFET}s and {\nFET} in the pull-up and pull-down networks, arbitrary
inverting logic functions of multiple inputs can be similarly implemented.
\setlength{\parindent}{\outerparindent}

(b) Dynamic behavior.  The {\nFET} conducts significantly when $V\tg{in}$
is above the threshold voltage $V\tg{Tn}$, and the {\pFET} conducts when
$V\tg{in}$ is below the level $V\tg{dd}+V\tg{Tp}$ (where $V\tg{Tp}$ is
negative).  When the input voltage $V\tg{in}$ goes to the high level
$V\tg{dd}$, representing a logic {\onebit}, the output voltage $V\tg{out}$
goes to the low level of $0\;\Volt$, representing a {\zerobit}, and
vice-versa.  The delay $t\tg{d}$ is affected by the {\defn{load
capacitance}} $C\tg{L}$, the supply and threshold voltages, and the
{\defn{gain factors}} (also called {\defn{device transconductance
parameters}}) $k\tg{n}$ and $k\tg{p}$ of the {\nFET} and {\pFET} devices.
If the inverter is driven by a similar inverter and if $k\tg{p}\approx
k\tg{n}$, then the rise and fall times $t\tg{r}$ and $t\tg{f}$ of input and
output will be about equal.}
\label{fig:inv}
\vspace{0.1in}
\hrule
\end{figure}

The inverter structure can be generalized to compute any {\defn{inverting}}
boolean function of many inputs (a one-bit function that is monotonically
non-increasing in the values of the input bits), by replacing the {\pFET}
and {\nFET} with appropriate networks of many {\pFET} and {\nFET} devices,
respectively.

Now, suppose we wish to minimize the total entropy generation of a
computation.  To see how to do this, let consider how energy dissipation in
a CMOS circuit scales with various parameters.

\subsubsection{iCMOS energy dissipation}
\label{sec:icmosdiss}

We have seen that standard CMOS circuits charge and discharge loads by
connecting them to constant-voltage power supplies.  Because of this,
whenever the voltage of a node is switched from one level to another,
through a voltage change $V$, the energy dissipated is at least
$\frac{1}{2}CV^2$, where $C$ is the total capacitance being switched.

To understand this, refer to fig.~\ref{fig:switch}.  An amount $Q=CV$ of
charge is delivered to the node from voltage $V$, so the energy supplied is
at least $E\tg{supp} = QV = CV^2$.  The energy stored on the node is
\begin{eqnarray*}
E\tg{stor} &=& \int dE = \int \label{pg:vinst}v(q)\,dq = \int \frac{q}{C}\,dq
		= \frac{1}{C} \int_0^Q q\,dq\\
	&=& \frac{1}{C}\,\left.\frac{1}{2}q^2\right|_{q=0}^Q
		= \frac{1}{2C} Q^2 = \frac{1}{2C} (CV)^2\\
	&=& \frac{1}{2} CV^2.
\end{eqnarray*}
(For additional textual explanation, see {\cite{SeZeYo84}}, {\S}27-4,
p.~521.)  The remaining energy $E\tg{supp}-E\tg{stor} =
CV^2-\frac{1}{2}CV^2 =
\frac{1}{2}CV^2$ can not be accommodated in the circuit model; no
matter the precise mechanism by which it has left the system, this energy
is now considered unmodeled, statistical, thermalized; so as a matter of
definition we call it ``dissipated.''  Essentially it becomes heat.

\begin{figure}
\centerline{\psfig{file=switch.epsi,width=3in}}
\caption[Energy dissipation in conventional switching]{Energy dissipation
in conventional switching.  Whenever a node is switched by connecting it to
a constant-voltage $V$ power supply, such as occurs in the ordinary CMOS
gate of fig.~\ref{fig:inv}, the transfer of the charge $Q=CV$ from the
constant-voltage source to the node capacitance $C$ results in an energy
dissipation of $\frac{1}{2}CV^2$, where $V$ is the voltage swing and $C$ is
the capacitance being switched.}
\label{fig:switch}
\vspace{0.1in}
\hrule
\end{figure}

This energy dissipation and the accompanying entropy increase occurs under
{\emph{any}} means of setting a voltage by delivering charge directly from
a constant-voltage source.  There is no way it can be avoided by, for
example, simply adjusting the resistance or inductance of the switch: note
that the above analysis depends in no way on such parameters.  We call this
$\frac{1}{2}CV^2$ dissipation the {\defn{switching energy}} $E\tg{sw}$.

Of course, if the circuit is a small part of a larger system, then the
dissipation to heat of a certain amount of energy by the circuit need not
imply that this energy will never again be available for work: for example,
given a cool thermal reservoir, the computer can, as a side effect, power a
heat engine which can recover a portion of the dissipated energy as work.
But in the absence of any specific mechanism tailored to capture the
supplied energy in a more direct way, the energy $E=\frac{1}{2}CV^2$ must
at still at least be {\emph{temporarily}} dissipated (thermalized), which
results in an immediate, irreversible entropy generation of at least
$S=CV^2/2T$, where $T$ is the temperature of the circuit.

Moreover, if the switch that we are using is a static CMOS logic gate,
there may be additional dissipation in the gate if the {\nFET} and {\pFET}
are simultaneously conducting significantly during some portion of the
input transition, resulting in a current from power to ground through both
transistors.  Generally this will occur if $\Vdd\gtrsim
V\tg{Tn}+|V\tg{Tp}|$.

This {\defn{short-circuit dissipation}} is somewhat more complex to model
than switching energy, because it depends on the dynamic behavior of the
CMOS devices and the input signal.  But we can make some useful
approximations when the input is driven by a similar gate: if $\Vdd\gg
V\tg{Tn}+|V\tg{Tp}|$, then a rough dynamic analysis shows that the
short-circuit dissipation $E\tg{ss}$ will be around $CV\tg{dd}^2$,
comparable to the switching energy.  However, if $V\tg{dd}\lesssim
V\tg{Tn}+|V\tg{Tp}|$, then the short-circuit dissipation will be small
compared to the switching energy.

Finally, for sufficiently slowly-switching CMOS circuits, another source of
dissipation may become important, namely leakage energy due to
sub-threshold conduction of MOS devices even when turned off.  Due to
thermal effects, the transistor off-current cannot be made less than the
on-current by more than a factor of roughly $f = e^{\Vdd/\Vth}$, where
$\Vth=\kB T/\ech$ is the thermal voltage of electrons in a device at
temperature $T$.  Therefore when device idle times are more than a factor
of $f$ times larger than switching times, the {\defn{leakage energy}}
$E\tg{leak}$ due to the off-current may be the dominant contributor to the
total energy dissipation per operation.

\subsection{iCMOS entropy generation.}
\label{sec:cmosentgen}
All of the total energy $E\tg{tot} = E\tg{sw}+E\tg{ss}+E\tg{leak}$
dissipated per operation, due to these various causes, becomes heat,
generating an amount of new entropy $S = E\tg{tot}/T$, where $T$ is the
operating temperature of the devices.  This entropy generation can be made
smaller by raising the operating temperature, but only up to a point,
because higher temperatures eventually lead to large leakage currents, and
higher operating voltages (because we must obey $\Vdd\gtrsim\Vth$ or
else transistors will not be significantly more conductive when on than
when off), and will eventually preclude correct functionality altogether,
by melting the device, if not by some other effect that cripples the
device's functionality far below its melting temperature.

The relationships between all these factors are complex, but if we just
assume that there is some maximum temperature $T\tg{max}$ for a
working CMOS device, and if as an initial rough estimate we place
$T\tg{max}$ at around 150 degrees Celsius (423 K) (we do not know of any
semiconductor chips that operate hotter than this), then this gives us a
rough lower bound on entropy generation of $S\geq\frac{1}{2}CV^2/(423 K) =
\e{1.18}{-3} CV^2/K = (86\units{\nat/aJ}) CV^2$, which is an unavoidable
lower bound as long as $C$ and $V$ are assumed fixed.

We can still lower bound the entropy generation even if $V$ is allowed to
vary.  Since we know that $V\gtrsim\Vth=\kB T/\ech$ for correct
functionality, we can define a new lower bound in terms of temperature and
load capacitance:
\begin{eqnarray*}
S &\geq& \frac{1}{2}CV^2/T\\
  &\gtrsim& \frac{C(\kB T/\ech)^2}{2T}\\
  &=& \frac{C\kB^2 T}{2\ech^2}.
\end{eqnarray*}
Or, if we define a quantity $\Cth\defas \ech/\Vth$, which we will call the
{\defn{thermal capacitance}}, we have
\begin{equation}
S \gtrsim \frac{1}{2}\cdot\frac{C}{\Cth}\units{nat}.\label{eq:S-vs-C}
\end{equation}

For example, at a temperature of 300 K (room temperature), the thermal
capacitance is $\Cth\approx\e{6.2}{-3}\units{fF}$, so our entropy bound
becomes
\[
S \gtrsim (80.7\units{nat}/\unit{fF})\ C.
\]
Since $\Vth\propto T$, $\Cth\propto 1/T$ and so the minimum $S$
in~\eqref{eq:S-vs-C} scales as $T$, showing that actually, when voltage is
adjustable, low temperatures are best for minimizing entropy generation, at
least until the point where the minimum $\Vdd$ is no longer limited only by
the thermal voltage.

The form of eq.~\eqref{eq:S-vs-C} might seem to suggest that ordinary
static CMOS circuits could theoretically generate less than a bit of
entropy per switching operation, at any given temperature, if the node
capacitance is just made sufficiently small compared to the thermal
capacitance.  However, we will now see that the capacitance and voltage
{\emph{cannot}} together be made low enough to generate less than 1 bit of
entropy per switching event, while still permitting reliable operation of
these irreversible circuits.

What is the interpretation of the thermal capacitance $\Cth$?  First, from
our above definition, it is the node capacitance for which at least 1/2 nat
of entropy is generated by dissipative switching through a voltage swing of
$\Vth$.  But it is also the node capacitance at which the addition of
{\emph{one electron}} raises the node voltage by $\Vth$.  Since individual
electrons experience an average excitation equal to the thermal energy
$\Eth = \kT$, the voltage on a node with capacitance only $\Cth$ will
routinely be different than the expected level by amounts comparable to the
thermal voltage.  Therefore such a node cannot reliably store a logic value
encoded by a voltage difference of only $\Vth$.  For that, a significantly
greater capacitance is required.

Additionally, switching a node by tying it to a constant-voltage source at
voltage $V$ is a logically irreversible operation, since after the
transition is completed, the information about the previous logical state
of the node has been lost.  (There is simply no mechanism in these simple
circuits for retaining this information in a controlled form, just as there
is no mechanism, for the $\frac{1}{2}CV^2$ of supplied energy that doesn't
end up on the capacitor, of retaining that energy in a controlled form,
{\ie}, not heat.)  So, if the node was equally likely to be in either of
two states before the operation, one of them at voltage $V$ and the other
at voltage $0$, and after the operation it is reliably in a single state
(corresponding to voltage $V$) then the average entropy generation is at
least $1\units{bit}=\ln 2\units{nat}$.  Thus the average energy dissipation
must be $\kB T\ln 2$ to provide for this entropy (see~\S\ref{sec:SandE},
p.~\pageref{sec:SandE}).

Since no energy is dissipated in the half of the cases when the node is
unchanged, the energy dissipation in the other half of the cases must be
twice this, $2\kB T\ln 2$, in order for the average dissipation to be $\kB
T\ln 2$.  In order for the switching energy $\frac{1}{2}CV^2$ to be greater
than this, we must have
\begin{eqnarray*}
\frac{1}{2}CV^2 &\geq& 2(\ln 2)\kB T = 2(\ln 2) \Eth\\
C &\geq& 4(\ln 2)\frac{\Eth}{V^2}
\end{eqnarray*}
so if $V\approx\Vth$,
\begin{eqnarray*}
C &\gtrsim& 4(\ln 2)\frac{\Eth}{\Vth^2}\\
  &=& 4(\ln 2)\,\Cth.
\end{eqnarray*}
For example, at $T=300\units{K}$, and $V\approx\Vth$, we have $C\gtrsim
0.017\units{fF}$.

In other words, the minimum average entropy generation per irreversible
switching event {\emph{must}} be
\[
S \geq 2\units{bits}
\]
if reliable erasure of a random bit is to be possible.

More generally, consider nodes in any constant-voltage switching technology
in which short-circuit energy and leakage energy are negligible, so that
the $\frac{1}{2}CV^2$ switching energy is the only dissipation.  Suppose a
node is to hold a logic {\onebit} in exactly one randomly-selected case out
of $N$ cases (instances distributed in space or in time), and is {\zerobit}
in the rest of the cases, and we wish that, with high probability, the
logic value should become {\zerobit} after the switching operation in
{\emph{every case}}, given that the node becomes tied to a constant voltage
source whose level represents {\zerobit}.  The entropy generated is
\begin{equation}
S\geq\ln N\units{nats}, \label{eq:Sforreli}
\end{equation}
but energy is only dissipated in the single case where the bit is
{\onebit}.  In order for the environment to hold the increased entropy, the
energy dissipated during switching in this case must be $E\geq ST\geq \kB
T\ln N$.  In other words, node capacitance $C$ and swing voltage $V$ must
be such that
\begin{equation}
\frac{1}{2}CV^2 \geq \Eth\ln N\label{eq:CV2lim}
\end{equation}
in order for a node to switch correctly in every one of $N$ instances (with
high probability).  Another way to write this formula is
\[
\frac{1}{2}\left(\frac{C}{\Cth}\right)\left(\frac{V}{\Vth}\right)^2
\geq \ln N,
\]
which shows explicitly the relationship between node capacitance, thermal
capacitance, node voltage, and thermal voltage.  If we take $V\approx\Vth$,
we get a lower bound on node capacitance of
\[
C\gtrsim 2(\ln N)\,\Cth.
\]
So, for example, to achieve a nice $N$ value of $10^{27}$, corresponding to
a computer with $10^9$ circuit nodes not making a single thermal error in
$1\units{Gs}$ ($\about 32$ years) of operation at a clock speed of 1 GHz,
we must have a capacitance {\emph{per circuit node}} of $C\gtrsim
0.77\units{fF}$, if the operating voltage is almost as low as the
room-temperature thermal voltage.  Present-day gate capacitances of
minimum-sized transistors are already near these levels.  If some circuit
nodes actually have smaller capacitances than this, supply voltages cannot
actually approach the thermal voltage without sacrificing reliability to
some extent.

It is interesting that we are able to derive the above relationship between
reliability and node capacitance solely on the basis of the entropy
generation and the switching energy.  This can be compared with the
traditional approach of developing a sophisticated thermal noise model,
which finds that voltage samples follow a normal distribution, with a mean
squared error (on a capacitance-$C$ node) of ${\Delta V}^2 = \kB T/C$\label{pg:kToverC}
(\cite{MotchConn-93}, {\S}1.12, p.~31), and therefore to sample $N$
instances to an accuracy of $\kB T$ with high reliability, $C$ must scale
up with $\ln N$ roughly as we have described, or else there will be a
significant chance that a thermal fluctuation will, in one of the $N$
instances, place the voltage sample enough standard deviations out on the
tail of the distribution to cause a sampling error, and thus qualitatively
incorrect functionality of the logic.  {\ed{Need a book with a derivation
of the thermal reliability of A-to-D conversion, to reference.}}

\subsubsection{Voltage bounds.}
\label{sec:vbound}

To express the above voltage bound quantitatively, we can rewrite
eq.~\eqref{eq:CV2lim} as a lower bound on the swing voltage $V$ in terms of
the node capacitance and thermal constants:
\[
V\geq \sqrt{\frac{2 \Eth \ln N}{C}}
\]
or equivalently
\[
V\geq \Vth \sqrt{2\ln N \frac{\Cth}{C}}.
\]

Thus, as capacitances decrease towards and below the thermal
capacitance~$\Cth$, minimum node swing voltages must increase to larger and
larger multiples of the thermal voltage, proportional to the square root of
the capacitance decrease, in order to maintain a given level of
reliability.  This is an important lower bound on operating voltage which
must be taken into account when considering the minimum energy dissipation
of irreversible switching circuits.

Of course, continually increasing voltages in order to shrink circuits is
unrealistic since high electric fields will cause gate oxide breakdown.  So
in the long term, as nodes shrink in all dimensions proportionally to some
characteristic feature size $\ell$, and node capacitances and voltages
decrease proportionally, the above analysis really demands that we must
eventually start scaling switching energy down as $CV^2 \exactly \ell^3$
(which is intuitive for another reason, namely that otherwise, assuming
switching frequency does not decrease, the power dissipation density in the
channel would increase indefinitely, which would eventually cause damage
such as melting and loss of structure) and the only way to reduce the
switching energy in an irreversible circuit while still maintaining thermal
reliability is, by the above analysis, to scale the temperature down with
$\ell^3$ as well.  So as trends in irreversible circuits continue, active
cooling to cryogenic temperatures will eventually become a necessity in
order to maintain good reliability.

Another lower bound on operating voltage for CMOS circuits comes from the
fact that the device thresholds $V\tg{Tn}$ and $V\tg{Tp}$ cannot be set
with complete precision, due to the statistical nature of existing dopant
implantation processes.  If $V\tg{dd}$ is not significantly larger than the
variability $\sigma\tg{VT}$ of the $V\tg{T}$ values, then some devices may
fail to switch on and off as desired, and functionality may be compromised.

Our lower bounds on operating voltage may be summed up as follows:
\begin{align*}
V & \gtrsim \Vth 
	&& \text{(to switch FETs strongly on and off)}\\
V & \geq    \Vth \sqrt{2\ln N \frac{\Cth}{C}}
        && \text{(for reliability despite thermal noise)}\\
V & \gg     \sigma\tg{VT} 
        && \text{(to avoid defects due to threshold variation)}. 
\end{align*}

Actually operating at the minimum voltage that is permitted by the above
requirements may or may not maximize cost-efficiency, depending on the
particular measure of cost that we are trying to minimize.  Let us now see
how to choose the operating voltage of irreversible static CMOS circuits so
as to maximize efficiency under a variety of cost measures.

\noheading
To sum up our discussion of entropy generation in irreversible CMOS, we saw
that one should arrange that $\frac{1}{2}CV^2$ for each switching event is
as small as possible, while remaining above $\Eth\ln N$ (see
eq.~\ref{eq:CV2lim}).  Lowering the operating temperature helps decrease
entropy production if it allows $V$ to decrease.  If
$\frac{1}{2}CV^2=2\Eth\ln N$, then entropy generation must be at least $\ln
N$ nats per switching event.  This is $\alpha N\ln N$ nats for an
error-free computation composed of $N$ primitive operations, if a fraction
$\alpha$\label{p:swfrac} of the operations cause switching.

Of course, other technological considerations may prevent $\frac{1}{2}CV^2$
from coming anywhere close to room-temperature $\Eth$.  The minimum load
capacitance is determined by factors such as the minimum transistor gate
area, and $V$ is independently bounded below by the variability
$\sigma\tg{VT}$ of device threshold voltages due to the statistical nature
of ion implantation in the channel region.  An interesting property of any
given CMOS fabrication process is the ration between the minimal
$\frac{1}{2}CV^2$ and $E_{\temperature=300\unit{K}}$ in
properly-functioning logic circuits in that process.  In~\S\ref{sec:SIA} we
estimate this quantity for several present and projected future generations
of CMOS technology.

\subsection{The SIA semiconductor roadmap}
\markright{\thesubsection. THE SIA SEMICONDUCTOR ROADMAP}
\label{sec:SIA}

Table~\ref{tab:SIA} shows some parameters for future generations of CMOS
VLSI technology as forecasted by the Semiconductor Industry Association, in
{\cite{SIA-97}}.  We will be referring to these numbers for our
calculations throughout the rest of this section.

\begin{table}
\begin{minipage}{\textwidth}
\begin{tabular}{|l|c|c|c|c|c|c|c|}\hline
	& \multicolumn{7}{|c|}{\textbf{Year of first product shipment}} \\
	\cline{2-8} & 1997 & 1999 & 2001 & 2003 & 2006 & 2009 & 2012 \\
\hline\hline
\multicolumn{8}{|l|}{\textbf{Overall characteristics:}} \\
\hline
Trans. density,\footnote{Logic transistor density in a packed,
high-volume, cost-performance microprocessor, including on-chip SRAM.
From {\cite{SIA-97}}, p.~14.} 
	& $3.7$ & 6.2 & 10 & 18 & 39 & 84 & 180 \\
\ \ $10^6\units{trans}/\cm^2$ &&&&&&&\\
\hline
Chip size,\footnote{Size for a \micro processor, year 1, before subsequent shrinks;
{\cite{SIA-97}} p.~15.} $\mm^2$ 
	& 300 & 340 & 385 & 430 & 520 & 620 & 750 \\
\hline
Clock freq.\footnote{On-chip local clock frequency for high-performance
chips, {\cite{SIA-97}}, p.~16.}, {\unit{GHz}}
	& 0.75 & 1.25 & 1.5 & 2.1 & 3.5 & 6 & 10 \\
\hline
Supply voltage\footnote{Minimum logic power supply voltage $\Vdd$,
{\cite{SIA-97}}, p.~17.}, V
	& 2.5--1.8 & 1.8--1.5 & 1.5--1.2 & 1.5--1.2 & 1.2--.9 & .9--.6 &
	.6--.5 \\
\hline
Max. power\footnote{Maximum power consumption for a high-performance
processor with heat sink, {\cite{SIA-97}} p.~17.}, W
	& 70 & 90 & 110 & 130 & 160 & 170 & 175 \\ \hline
\multicolumn{8}{|l|}{\textbf{Technology requirements:}} \\ \hline
\micro P drawn channel 
	 & 200 & 140 & 120 & 100 & 70 & 50 & 35 \\
\ \ length\footnote{Minimum feature sizes, {\cite{SIA-97}},
pp.~14, 85.\label{ft:fsize}}, nm &&&&&&&\\
\hline
DRAM $\frac{1}{2}$-pitch$^{\text{\ref{ft:fsize}}}$, nm
	& 250 & 180 & 150 & 130 & 100 & 70 & 50 \\
\hline
$T\tg{ox}$ equivalent\footnote{The last four lines in the table are all from {\cite{SIA-97}}, p.~46.\label{ft:p46}}, nm
	& 4--5 & 3--4 & 2--3 & 2--3 & 1.5--2 & $<1.5$ & $<1$ \\
\hline
$CV/I$ delay$^{\text{\ref{ft:p46}}}$, ps
	& 16--17 & 12--13 & 10--12 & 9--10 & 7 & 4--5 & 3--4 \\
\hline
$V\tg{T}$ $3\sigma$ varia.$^{\text{\ref{ft:p46}}}$, $\pm\unit{mV}$
	& 60 & 50 & 45 & 40 & 40 & 40 & 40 \\
\hline
Src./drn. junction 
	& 50--100 & 36--72 & 30--60 & 26--52 & 20--40 & 15--30 & 10--20 \\
\ \ depth,$^{\text{\ref{ft:p46}}}$ nm &&&&&&&\\
\hline
\end{tabular}
\caption[SIA semiconductor roadmap]{Selected numbers from the 1997
edition of the Semiconductor Industry Association's national semiconductor
roadmap {\cite{SIA-97}}.  These numbers are used for the calculations in
tables~\ref{tab:SIAentropy} and \ref{tab:SIA-AT}.}\label{tab:SIA}
\end{minipage}
\vspace{0.1in}
\hrule
\end{table}

Given these numbers, we can take a stab at an actual numeric computation of
the minimum entropy generation per switching event.  See
table~\ref{tab:SIAentropy}.  Let us explain these calculations.

\begin{table}\centering
\begin{tabular}{|l|c|c|c|c|c|c|c|}\hline
				& \multicolumn{7}{|c|}{\textbf{Year of first product shipment}}\\
				\cline{2-8}	
				& 1997	& 1999	& 2001	& 2003	& 2006	& 2009	& 2012	\\
\hline\hline
\multicolumn{8}{|l|}{\textbf{Capacitance calculations:}} \\
\hline
Gate oxide thickness
$\tilde{T}\tg{ox}$, $\unit{nm}$	& 4.5	& 3.5	& 2.5	& 2.5	& 1.75	& 1.5	& 1	\\
Gate areal capac.\ 
$C\tg{ox}$, $\unit{fF}/\um^2$	& 7.81	& 10.0	& 14.1	& 14.1	& 20.1	& 23.4	& 35.1	\\
Min.\ gate cap.\ 
$C\tg{gmin}$, $\unit{aF}$	& 312	& 197	& 202	& 141	& 98.4	& 58.6	& 43.0	\\
Est.\ min.\ load cap.\ 
$\tilde{C}\tg{Lmin}$, $\unit{fF}$& 5.00	& 3.15	& 3.24	& 2.25	& 1.57	& .937	& .689	\\
\hline
\multicolumn{8}{|l|}{\textbf{Voltage calculations:}} \\
\hline
Transistors/die, $10^6$		& 11.1	& 21.1	& 38.5	& 77.4	& 203	& 521	& 1350	\\
$N$ trans./defect (90\pct\ yield), $10^9$&.111&.211 & .385	& .774	& 2.03	& 5.21	& 13.5	\\
Defect probability $p$, $10^{-9}$& 9.01	& 4.74	& 2.60	& 1.29	& .493	& .192	& .0741	\\
Number $n$ of $\sigma\tg{VT}$'s	& 5.75	& 5.86	& 5.96	& 6.07	& 6.23	& 6.37	& 6.52	\\
Est.\ min.\ $V\tg{dd}$:
$\tilde{V}\tg{min}$, $\unit{mV}$& 230	& 195 	& 179	& 162 	& 166	& 170	& 174	\\
\hline
\multicolumn{8}{|l|}{\textbf{Energy and entropy:}} \\
\hline
Switching en.\ 
$E\tg{sw}=\frac{1}{2}CV^2$, $\unit{aJ}$ & 132  & 59.9 & 51.9 & 29.5 & 21.6 & 13.5 & 10.4 \\
Est.\ min.\ ent.\ 
$\tilde{S}\tg{min}$, $\unit{knat}$      & 23.9 & 10.8 & 9.40 & 5.35 & 3.92 & 2.45 & 1.89 \\
Inefficiency factor		        & 385  & 174  & 151  & 86.0 & 63.0 & 39.4 & 30.4 \\
Min.\ perm.\ energy loss, $\unit{aJ}$	        & .903 & .409 & .354 & .202 & .148 & .092 & .071 \\
\hline
\end{tabular}
\caption[Minimum entropy generation for irreversible CMOS]
{Calculations of minimum capacitance, supply voltage, energy dissipation,
and entropy generation for irreversible CMOS, based on the SIA roadmap data
from table~\ref{tab:SIA}.  The minimum entropy generation per switching
operation that is required given a 90\pct\ die yield ranges from 24
kilonats to 1.9\units{knats}, which is greater than that required for a
thermal reliability of less than 1 error in $10^{27}$ switching operations,
by factors ranging from 385 in current technology, to 30 in projected
technology for the year 2012.}
\label{tab:SIAentropy}
\vspace{0.1in}
\hrule
\end{table}

First, we perform some calculations to work towards finding out the load
capacitance of typical small but non-trivial logic nodes (\eg, NAND gates
with output fanning out to 4 similar NAND gates) in each technology
generation.  This is important because we observed earlier that the lower
bound on entropy generation is affected by load capacitance.

\paragraph{Estimated gate oxide thickness.}  
We derive an estimate $\tilde{T}\tg{ox}$ for the gate oxide thickness in
each technology generation by taking the average of the high and low values
given by SIA, or the high value if no low value is given.

\begin{tab}
\begin{tabular}{|l|l|l|}
\hline
Symbol			& Approximate value
				& Meaning \\
\hline\hline
$\epsilon_0$		& $8.85\units{aF/\um}$ 
				& Dielectric constant of vacuum \\
$\epsilon\tg{Si}$	& $11.7\epsilon_0 \approx 105\units{aF/\um}$ 
				& Dielectric constant of silicon\\
$\epsilon\tg{ox}$	& $3.97\epsilon_0 \approx 35.1\units{aF/\um}$ 
				& Dielectric constant of $\mathrm{SiO_2}$\\
\hline
\end{tabular}
\caption[Dielectric constants]{Some important dielectric constants for 
semiconductor electronics calculations.
Taken from the frontispieces of {\cite{Hodges-Jackson-88,Rabaey96}}.}
\label{tab:econstants}
\end{tab}

\paragraph{Gate capacitance per unit area.}
The dielectric constant of SiO$_2$ (see table~\ref{tab:econstants}) is
$\approx 351\units{fF/cm}$.  If we divide this by $\tilde{T}\tg{ox}$, we
get per-area gate capacitances $C\tg{ox}$ ranging from 7.81\units{fF/\um^2}
up to 35.1\units{fF/\um^2} as the technology improves.

\paragraph{Minimum gate capacitance.}
The gate-to-channel capacitance $C\tg{gmin}$ of a min\-i\-mum-sized
transistor can be calculated from $C\tg{ox}$, SIA's minimum gate length,
and a minimum width which is assumed to be equal to the minimum length; we
find values ranging from 312\units{aF} in 1997 to only 43\units{aF} in
2012.

\paragraph{Estimated load capacitance.}
In a minimum-size static CMOS NAND gate adjusted so that the effective gain
factor $k$ of pull-up and pull-down networks are equal to the minimal
transistor gain factor in the worst case, {\nFET} and {\pFET}s will both be
sized to about double the minimum width---the {\nFET}s because two of them
are in series, the {\pFET}s because hole mobility is only about half of
electron mobility.  An input impinging on the NAND feeds to one transistor
of each type, so the load placed on the input by the NAND is about 4 times
the minimum gate capacitance, plus fringing capacitances which we will
ignore.  If the output of each NAND gate fans out to about 4 other NAND
gates, then the total load capacitance on the NAND output is only about 16
times the minimum gate capacitance.  There is also a contribution from
wiring and from the source-drain regions of the gate generating the signal,
but if wire lengths are kept short, this can be absorbed into the factor of
4 without decreasing fan-out very much.  So based on this, we just multiply
$C\tg{gmin}$ by 16 to find an estimated load capacitance $\tilde{C}\tg{L}$
ranging from about 5 femto-Farads in 1997, to 0.69\units{fF} in 2012.

\paragraph{Transistors per die.}
From SIA's figures for transistor density and chip size, we can calculate
the total number of transistors per chip.  It ranges from 11 million up to
1.35 billion.

\paragraph{Transistors per defect.}
Suppose we require that the loss in die yield due to random threshold
variations should be less than 10{\pct}.  That is, less than one die in 10
should contain any transistor having a large enough error in its threshold
value to cause the transistor not to be in the correct (on vs.\ off) state
when required.  Multiplying by the transistors per die gives us the number
$N$ of transistors that need be produced on average before one is produced
that has such a defect.  That is, in a set of $N$ transistors, the expected
number of defects should be 1.  We might call this $N$ the {\defn{process
reliability number}}.  Values range from $\frac{1}{10}$ billion to 13.5
billion, as the number of transistors per chip increases in the SIA
projections.

\paragraph{Defect probability.}
The sum of expectation values over a set of independent events is additive.
So if the expected number of defects in $N$ transistors is 1, and the
statistical results of ion implantation in different transistors is
independent (a plausible assumption), the expected number of defects in 1
transistor must be $1/N$.  Thus the probability $p$ that a given transistor
will have a defect must be $1/N$.  The required defect probabilities thus
range from $\e{9}{-9}$ to $\e{74}{-12}$ as the transistor count increases.

\paragraph{Number of $\boldsymbol\sigma\tg{VT}$s required.}
Roughly speaking, an {\nFET} in static CMOS will cause incorrect
functionality either if it does not turn on when $V\tg{GS}$ is $V\tg{dd}$,
or if it does not turn off when $V\tg{GS}$ is zero.  Therefore variation in
thresholds should leave the threshold within the range $0\units{V}$ to
$V\tg{dd}$.  To minimize $V\tg{dd}$ for a given level of threshold
variability while remaining within reliability constraints, the nominal
$V\tg{Tn}$ should be exactly halfway between $0\units{V}$ and $V\tg{dd}$,
so that the transistor only fails if variation places the actual $V\tg{Tn}$
far out on one of the tails of the threshold distribution.  In this
situation, if the total probability of $V\tg{Tn}$ being out on the tail in
both directions is $p$, then the probability for either side (too high or
too low) is $p/2$, since these events are mutually exclusive.  (Similarly
for {\pFET}s.)

Given a probability of being out on one tail of at most $p/2$, we can
compute a lower bound on how many $\sigma\tg{VT}$s are required before we
are far enough out from the mean $V\tg{T}$ so that the total probability of
being that far out is no more than $p/2$.  In a normal distribution, the
total probability $\mathfrak{R}(n)$ of being at least $n$ $\sigma$s away
from the mean in a particular direction is bounded above as
\begin{equation}
\mathfrak{R}(n)\leq\frac{1}{n} \cdot \frac{1}{\sqrt{2\pi}}e^{-n^2/2}.\label{eq:tail}
\end{equation}
And in fact, in the limit of $n\rightarrow\infty$\label{pg:infty}, the probability out on
the tail approaches this value exactly (\cf\ Feller 1950
{\cite{Feller-50}}, ch.~VII, p.~175, eq.~(1.8).)

Therefore, to have $\mathfrak{R}(n)\leq p/2$, we only require that $n$ be
greater than or equal to the value given by solving
\[
2/p = \sqrt{2\pi}\cdot n e^{n^2/2}
\]
for $n$, which for given $p$ we can easily do numerically by computer using
Newton's method.  For our $p$'s we find values of $n$ ranging from $5.75$
to $6.52$ $\sigma\tg{VT}$s; this relatively narrow range is afforded by the
roughly exponential decay of the tail of the normal distribution.

\paragraph{Minimum $\boldsymbol{V\tg{dd}}$.}  Now we are finally in a position to
actually calculate the minimum value of $V\tg{dd}$ for each technology
generation.  With $V\tg{dd}= 2 |V\tg{T}|$, we must have $V\tg{dd}\geq
2n\sigma\tg{VT}$ in order for the total probability of an error-inducing
threshold defect (either too high or too low) to be less than $p$.  Given
SIA's values for $3\sigma\tg{VT}$, this yields minimal $V\tg{dd}$ voltages
ranging between 230\units{mV} and 162\units{mV}.

These values are all several times greater than the thermal voltages of
26--34\units{mV} found at normal operating temperature, so transistors that
are turned off will conduct several times less current than ones that are
turned on (in the worst case, we estimate, by at least a factor of 3),
meaning that correct functionality is maintained, and leakage does not
contribute very much to energy dissipation in circuits that switch
frequently.  However, if much lower levels of threshold variability than
those given in the SIA roadmap were to be attained, low-temperature
operation would be required in order for transistors to be able to turn off
sufficiently at the implied lower voltage levels; this would tend to
increase entropy generation, and thus reduce the advantages of the lower
energy dissipation.

\paragraph{Minimum energy/switching event.}  Given the minimum capacitance
of a useful logic node and a minimum swing voltage, we are now in a
position to calculate the minimum switching energy
$E\tg{sw}=\frac{1}{2}CV^2$ for such a node.

\paragraph{Minimum entropy/switching event.}  The minimum attainable
entropy is lower-bounded by the minimum energy divided by the maximum
temperature.  Raising the temperature has a variety of complicated effects
on CMOS device behavior, so this bound will not be exact.  But if we assume
that operating temperatures can't be much higher than, say,
$127^\circ\unit{C}$ (400\units{K}) while preserving correct functionality,
we can get a rough lower bound on entropy generation.

\paragraph{Inefficiency factor.}  Suppose we wish the probability of a
thermally-induced error to be $10^{-27}$ (this would correspond to, for
example, a billion logic nodes switching at 1 gigahertz with only 1 error
expected per gigasecond (31 years) of operation).  Then the number of nats
of entropy generation per switching event only needs to be $\ln 10^{27}
\approx 62.2$ in an ideal switching circuit.  So our CMOS circuits are
generating more entropy than the ideal switching circuits by factors
ranging from 385 down to 30.  So, thermal reliability does not become the
limiting factor on voltages for the foreseeable future of irreversible
CMOS, although if the technology could continue to be improved for several
more generations beyond the 2012 technology, this might change.

\noheading
This concludes our discussion of the minimum entropy generation per
operation attainable in irreversible CMOS circuits.  In summary, entropy
generation per switching event is expected to be greater than 1.8 kilonats
through at least the year 2012.  Insofar as each logic gate operation
involves about one switching event, this also corresponds roughly to the
entropy generation per primitive operation.

Even if unforeseen technological breakthroughs were to undercut this limit,
an entropy generation of at least {\emph{tens}} of nats per operation is
required in order for correct voltage-switching to occur with high
reliability in {\emph{any}} irreversible switching technology, due to the
argument that led to eq.~(\ref{eq:Sforreli}), p.~\pageref{eq:Sforreli}.

\subsection{Minimizing permanent energy dissipation in iCMOS}
\markright{\thesection.  MAXIMIZING THE EFFICIENCY OF ICMOS}
\label{sec:minloss}

Note that the energy dissipated by a CMOS circuit internally is {\emph{not
all lost}}.  If a circuit is maintained at a temperature $T\tg{H}$ that is
as high as allowed by reliability constraints, in order to minimize entropy
production, then most of the energy dissipated internally can be recovered,
by using the computer as the heat source for a Carnot-cycle heat engine
(\cf\ {\cite{SeZeYo84}}, \S19-6, p.~371--376) with a relatively
low-temperature reservoir at temperature $T\tg{L}\ll T\tg{H}$.  If the heat
is {\emph{emitted}} from the computer into the heat engine at temperature
$T\tg{H}$ ({\ie} no temperature degradation during transport), then a
fraction $(T\tg{H}-T\tg{L})/T\tg{H}$ of this heat can be converted to work
by the heat engine.

In other words, the total energy that is {\emph{really}} lost when $S$
entropy is generated is only $ST\tg{L}$.  If the $\about 2.73\units{K}$
cosmic microwave background can be used as the low-temperature reservoir,
then theoretically only $\about\e{4}{-23}\units{J}$ of energy need be
permanently lost for each bit of entropy generated in the computer, even
though a hundred times more energy than this is temporarily ``dissipated''
whenever circuit nodes switch.  This shows that energy dissipated in a
circuit does {\emph{not}} correspond to a permanent loss of work.  It is
only the {\emph{entropy}} generation of the computer that truly determines
the ultimate energy cost.

Thus, true energy loss is really minimized by minimizing entropy
generation.  If a $2.73 \units{K}$ reservoir is available, the minimum
energy loss for CMOS ranges from about 0.9\units{aJ} down to .07\units{aJ},
as shown in the last line of table~\ref{tab:SIAentropy}.

Actually, in practice there will always be some temperature degradation
during the transport of heat from the transistors to the heat engine input,
due to the non-infinite ``heat capacities'' of materials.  However, if this
temperature degradation is small compared to $T\tg{H}-T\tg{L}$, then the
above results will be approximately correct.

Also, in practice, the 3 K microwave background may not actually be readily
available as a thermal reservoir.  In this case, the ultimate reservoir
would be the atmosphere instead, and $T\tg{L}$ would be on the order of
$300 K$, and the minimum energies would be $\sim 100$ times higher.

\subsection{Maximizing per-area processing rate for iCMOS}
\label{sec:perarea}

Consider a cost measure like in~\S\ref{sec:ATprod}, consisting of the
rental cost of the land area or floor space required for a computation, or
in other words the surface area of the computer times the time taken by the
computation.  Suppose we wish to minimize that cost measure.

To do this, we would like to know how to maximize the rate of computation
that can be achieved per unit of surface area.  This rate is limited if
there is an upper bound on the rate of entropy removal through the machine,
and a lower bound on the entropy generated per operation.

To maximize the computation rate per unit of outer surface area in
irreversible CMOS, one should just maximize the ratio between the maximum
entropy flux $F\tg{S}$ in the cooling system and the entropy generation per
operation, then pack in enough layers of circuits below each unit of
surface area so that entropy is being generated at a rate per unit area
corresponding to $F\tg{S}$.

One key parameter to be chosen is the circuit operating temperature $T$.  A
lower operating temperature means more entropy generation for a given
energy dissipation, but also more entropy flux for a given heat flux; these
factors cancel out, meaning the relevant quantity is the ratio between the
maximum heat flux and the minimum energy dissipation.

However, lower temperature probably means a lower heat flux, since at least
some components of heat flow will increase with increased temperature
differences between inside and outside.  So within the bounds set by the
reliability requirements at a given operating voltage, the machine should
be operated as hot as possible.  This is also consistent with minimizing
the total entropy production, given the fixed lower bound on energy
dissipation in CMOS, and also with minimizing the total permanent energy
loss.

From SIA's figures for chip size and power, we can compute what heat flux
they are assuming.  If we take this as our maximum heat flux, we can
combine this with our calculated figures for the minimum energy dissipation
from table~\ref{tab:SIAentropy} to find the maximum rate of operation per
unit area.  See table~\ref{tab:SIA-AT}.

\begin{table}\centering
\begin{tabular}{|l|c|c|c|c|c|c|c|}\hline
				& \multicolumn{7}{|c|}{Year of first product shipment}	\\
				\cline{2-8}	
				& 1997	& 1999	& 2001	& 2003	& 2006	& 2009	& 2012	\\
\hline\hline
\multicolumn{8}{|l|}{Rate calculations} \\
\hline
Heat flux $F\tg{E}$, $\unit{W/cm^2}$
				& 23.3	& 26.5	& 28.6	& 30.2	& 30.8	& 27.4	& 23.3	\\
Max rate $\Rate\tg{pA}$, \units{ops/ns\rmh\um^2}
				& .882	& 2.20	& 2.76	& 5.13	& 7.09	& 10.1	& 11.2	\\
Min $A\Time$/op, $\unit{ns\,\um^2}$
				& 1.13	& .454	& .362	& .195	& .141	& .0986	& .0891	\\
\hline
%\multicolumn{8}{|l|}{Thickness calculations} \\
%\hline
%Area/NAND, $\um^2$		& 108	& 64.5	& 40	& 22.2	& 10.3	& 4.76	& 2.22	\\
%\hline
\end{tabular}
\caption[Outer-area times time, for irreversible CMOS]
{Calculations of heat flux, rate of operation per outer surface area, and
minimum outer-area rental cost per operation for (layered) irreversible
CMOS, based on the SIA roadmap data from table~\ref{tab:SIA}.  We find that
irreversible CMOS can at best perform only $\about$1--10 operations per
nanosecond per square micron of outer area, given the heat flux implied by
SIA's figures.  In other words, the area-time cost per operation in
$\unit{ns\,\um^2}$ units ranges from $\about1$ to $\about0.1$.}
\label{tab:SIA-AT}
\vspace{0.1in}
\hrule
\end{table}

What is the minimum thickness, in layers and in meters, for an irreversible
CMOS machine that achieves this maximum speed per unit area?  To determine
this, we need to know both the minimum area per logic gate, minimum circuit
layer thickness, and the maximum speed of operation of individual logic
gates when operating at the minimum voltage.

The minimum area per logic gate is easy to calculate from the SIA figures,
and an advanced wafer-thinning or SOI (silicon-on-insulator) process might
be expected to achieve a thickness per circuit layer as low as
{\about10\units\um} or less.

However, accurately determining the maximum speed of operation per gate
requires a more detailed analysis.  We would like to know an effective
resistance $\label{pg:resistance}R$ for our logic gates, when driven at our
minimized power supply voltage, such that in a characteristic time
$t_c\approx RC\tg{L}$ the output node is charged most of the way to the
desired voltage level.

Unfortunately, determining such an $R$ is rather complex.  First, the
instantaneous resistance of each MOSFET is not constant during node
charging; it varies as the drain voltage changes.  In multi-input logic
gates, some transistors will in general have varying source voltages as
well.  Moreover, the effective resistance of the active logic network
(pull-up or pull-down) will generally be data-dependent.  For example, the
pull-up network of a NAND gate, which consists of two transistors in
parallel, conducts best if both inputs are low, rather than just one being
low.  Finally, the instantaneous resistance depends on the supply voltage
in a complex way that depends on threshold voltage and source voltage, and
that in small devices is affected by a variety of difficult-to-model
short-channel effects, such as channel-length modulation, velocity
saturation, mobility degradation, and drain-induced barrier lowering ({\cf\
}{\cite{Toh-etal-88}} and \S2.3 of {\cite{Rabaey96}}).

We carried through a rough computation by hand (with help from the
{\texttt{Emacs calc}} tool) based on a model described in (Rabaey 1996,
{\cite{Rabaey96}}, {\S}2.3, p.~54, eqs.~(2.57)--(2.59)), and originally
proposed by Toh {\etal}\ (1988, {\cite{Toh-etal-88}}), which incorporates
threshold voltage, mobility degradation, and velocity saturation effects.
At this point we are still not completely confident in the accuracy of that
calculation, so we will not detail it here.  But one tentative result is
that when operating at the minimum supply voltages we derived earlier, we
end up with a maximum operation frequency that is only slightly higher than
those projected by SIA (it is within a factor of 2), although in our
analysis, the maximum operation frequency increases less rapidly than in
SIA's, as technology improves.  The reason for the remaining discrepancy
between our calculations and SIA's is unclear, and will probably remain so
until we obtain a fuller description of SIA's assumptions and analysis
methods.

Another tentative result of this analysis is that for maximizing total
computation rate per unit area, our choice of lower supply voltage results
in an overall speedup factor (compared to SIA's projections) that ranges
from 127 down to 2.5 as technology improves; part of the reason why the
improvement decreases seems to be that SIA's choice of supply voltage
converges from 10 times ours down to only 3 times ours, as the generations
progress.

Unfortunately, the low-voltage approach is not significantly more
cost-effective (in terms of rate per unit of silicon surface) than SIA's.
This is not surprising, since in these calculation we were not trying to
maximize overall cost-effectiveness, but rather only performance per unit
of outer area; we were ignoring the material cost of stacking up more
layers of surface over that area.  The number of circuit layers we need for
optimal per-area performance ranges from 80 (in 1997) down to 4 (in 2012),
and the cost of these extra layers roughly negates the benefit of the
increased performance.

\subsection{Maximizing iCMOS cost-efficiency}

When maximizing cost-efficiency in terms of circuit mass or wafer area,
rather than outermost-surface area, the analysis becomes more complex.  For
one thing, it depends on the nature of the computation to be performed.

If the computation consists of many small independent computations,
requiring only local communication in 2-D, for example, then the circuitry
can be spread out in a single layer, and the task is to maximize the rate
per unit of silicon area.  In this case, we are not entropy-limited, so we
cannot assume, as we did in the previous section, that the optimal
operating voltage is just the minimum voltage that is consistent with
reliability constraints.  Lower signal voltages in general increase the
effective resistance of transistors, and lead to longer charging times
$t\exactly RC$.  But the voltage cannot be too large either, or it will
cause oxide breakdown and other undesirable effects, and it could possibly
cause overheating even if the circuit is just a single layer.  An accurate
analysis would need to take these concerns into account, as well as all of
the complex short-channel effects that arise when scaling to smaller device
sizes.  Optimizing voltage in the face of all these concerns cannot be done
via solving a simple analytical equation; instead one must write a program
to search for the optimum point numerically.

Alternatively, if the computation requires frequent communication, such as
for example between neighboring cells in a 3-D mesh being simulated, then
the analysis is made complex for other reasons, namely because we cannot
spread everything out in a single layer without incurring communication
delays, as we discussed in ch.~\ref{ch:scaling}, {\S}\ref{sec:sim3d}.  If a
near-ballistic means for communication is available---such as an optical or
transmission-line system of interconnects between processors---then when
entropy generation becomes the dominant concern, the optimal structure is
the one from that earlier section, in which we lower the clock speed and
spread the processing elements out in proportion to the cube root of the
logical diameter of the communication network.

But in this case as well, carrying out the relevant calculations for future
generations of semiconductor technology would be complex and error-prone,
due especially to uncertainties in the technical specifications of the
communication network.

In both cases (2-D and 3-D computations), we will deem a detailed numeric
calculation of cost-efficiency to be beyond the scope of this thesis, and
we will relegate it to the domain of future work.  Still, such a
calculation will be important eventually, if we wish to be able to compute
the exact scale above which reversibility becomes advantageous, in each
succeeding technology generation.  In the current technology generation, a
very rough hand-calculation suggests that even in the most optimistic
scenario for reversible computing (namely, ballistic communication between
nodes at logical distance $\sqrt{\Ndiam}$, see {\S}\ref{sec:nonlocal},
p.~\pageref{sec:nonlocal}), reversibility doesn't improve cost-efficiency
until we reach a cost level on the order of
\dlr25 billion.  Later we will argue that over time, the case for
reversibility ought to improve, for as long as the $RC$ of CMOS technology
keeps improving; however, we will also argue that at some point, making
further $RC$ improvements will require moving to a radically different
technology, such as the superconducting Josephson-junction technology of
Likharev {\cite{Likharev-82}}.  In any case, making more accurate
projections of the advantages of reversibility in foreseeable generations
of CMOS technology would be very desirable in order to gauge the near-term
applicability of this research.

\noheading
This concludes our analysis of the best possible performance of normal
{\emph{irreversible}} CMOS circuits under various efficiency measures for
the foreseeable future.  This can serve as a baseline for comparison when
looking at reversible circuits.  {\ed{Originally I was planning to carry
through a detailed comparison, but doing this accurately is too hard to do
in a reasonable time.}}

Now, let us see how reversible circuit techniques came about.

\section{Historical development of adiabatic circuits}

We now review the historical development of reversible logic circuit
techniques.

\paragraph{Correcting an attribution.} Toffoli (1980, {\cite{Toffoli80}})
suggested that the idea of dissipationless computing using reversible
circuits originated with John von Neumann, but I have been unable to
confirm this claim.  To quote Toffoli's paper:
\begin{quote}
The idea that universal computing capabilities could be obtained from
reversible, dissipationless (and, of course, nonlinear) physical circuits
apparently first occurred to von Neumann, as reported in a posthumous paper
(Wigington 1961 {\cite{Wigington-61}}).
\end{quote}
However, based on a careful reading of Wigington's paper, I believe that
Toffoli's characterization of it is incorrect.

Wigington's\label{pg:wig} paper {\cite{Wigington-61}} is an explanation of
a patent {\cite{vonNeumann-57}} submitted by von Neumann in 1954 and
posthumously granted to him in 1957.  The paper describes a computing
scheme in which logic values are represented by the relative phase of AC
signals, rather than by the DC voltage level used in conventional systems.
Wigington also cites similar work (on ``Parametron'' circuits) that
apparently occurred around the same time in Japan.

The logic circuits that Wigington discusses do indeed include some elements
(namely, nonlinear reactances) that can be assumed to have arbitrarily low
dissipation (and whose operation is therefore physically reversible), but
the described circuits also include attenuators that are placed in the
signal paths {\emph{explicitly}} in order to dissipate the energy of
signals whose phase information is no longer needed, in exact analogy to
the practice in traditional DC logic circuits of dumping a node's static
energy through a dissipative switch whenever its logic value is no longer
needed.  Without these attenuators, von Neumann's circuits would not
reliably implement the computing scheme described.  In fact, the need for
dissipation is guaranteed by the logic system used.  The fundamental
logical operation in von Neumann's AC circuits is to take three binary
input signals, and from them generate a boolean output signal whose logic
value is the majority value of the inputs.  The input signals are consumed
in the process, in the attenuators.  Since the resulting operation is a
many-to-one transformation of the logical state of the circuit, it destroys
logical information, and thus {\emph{cannot}} be implemented in a
physically reversible way, by Landauer's argument ({\S\ref{sec:reverase},
p.~\pageref{sec:reverase}}).  No matter how we try to modify von Neumann's
circuit, we will fail to achieve dissipationless, reversible operation, so
long as the logical state transformation operation that is performed is a
many-to-one operation such as Wigington describes.

Therefore, Toffoli's characterization of the von Neumann/Wigington paper
seems mistaken.  Von Neumann had certainly had a great many original ideas
during his lifetime, and it is conceivable that he thought about the idea
of reversible, dissipationless computing, but if so, the Wigington paper
certainly provides no evidence to support that attribution.

\paragraph{Earliest adiabatic circuits.}
To our knowledge, the first description of a logic circuit technique that
seriously attempts to avoid the $\sim CV^2$ dissipation associated with
conventional logic is that of Watkins 1967 {\cite{Watkins-67}}.  Watkins
describes a technique whereby capacitive loads in a circuit are charged
gradually through the control transistors from a power supply whose voltage
fluctuates cyclically according to prescribed waveforms.  When the
transistors in Watkins' circuit are first turned on, there is no voltage
across them and thus no dissipation through them.  While the load is being
charged up through the transistor, there is a small voltage across it, and
thus some dissipation, but this dissipation can be made as low as desired by
just lengthening the time taken in the charging cycle.  Watkins analyzes the
energy dissipation in his circuit, and predicts that the energy per cycle
asymptotically approaches zero as the cycle time is increased.

Unfortunately, Watkins' energy analysis appears not to have been quite
correct, due to his use of semiconductor diodes to discharge the nodes in
his circuit.  Such diodes have an intrinsic voltage drop $\phi_T$ across
them (\cf {\cite{Kramer-etal-95}} {\S2} and {\cite{Rabaey96}} {\S}2.2.1,
p.~20) which does not decrease as the circuit is run more slowly.
Therefore, Watkins' circuits still incur a minimum dissipation of $\sim
CV\phi_T$ per operation, no matter how slowly they are run.  Therefore,
they do not qualify as truly {\emph{time-proportionately reversible}} (see
{\S}\ref{sec:tpra}, p.~\pageref{sec:tpra}) logic devices that could improve
asymptotic cost-efficiency as per the arguments in
chapter~\ref{ch:scaling}.  In any case, for whatever reason, Watkins'
proposal appears to have faded into obscurity.\footnote{According to
{\emph{Science Citation Index}}, Watkins' article {\cite{Watkins-67}} was
only cited a total of four times through 1976, and these citations appear
to all be from general review articles, rather than applications of
Watkins' research.  After 1976, Watkins was not cited at all until Bill
Athas and colleagues rediscovered his work in 1997 {\cite{Athas-etal-97}}.}

\paragraph{Inductor-based approaches.}
After Watkins, we next see the idea of dissipationless electronic logic
crop up independently in a 1978 proposal by Fredkin and Toffoli
{\cite{FredToff78}}.  In their idea, energy is shuttled around between
inductors and capacitors, but is not dissipated substantially, in a circuit
that implements a purely reversible primitive operation, namely a 3-input
3-output Fredkin gate.  The assertion is that in such a circuit, energy
dissipation can be made arbitrarily small if only the quality factor $Q$ of
the $LC$ elements can be made arbitrarily large.  Unfortunately, the
Fredkin-Toffoli approach was not immediately practical, because it appeared
to require large numbers of inductors, roughly one for each logic element,
whereas VLSI fabrication technology does not well support high-quality
integrated inductances.

However, in 1985 the ball was again picked up by Charles Seitz and
colleagues {\cite{Seitz-etal-85}} at Caltech, who (apparently
independently) describe a logic technique similar to Fredkin and Toffoli's,
but in which the inductances are instead shared between many logic
circuits, and are brought off-chip, and can therefore be implemented using
a technology that is more optimized for providing high-$Q$ resonance than
is VLSI.  The relatively complex switching circuitry that controls the
logical operation of the circuit remains integrated on-chip.  This was a
key step on the road to making resonant circuits practical.  However, Seitz
{\etal} only worked out the technique in detail for relatively simple
circuits; they leave open the question of whether a general logic family
could be worked out to implement {\emph{any}} combinational or sequential
logic with arbitrarily little dissipation.  Their proposed solution is, in
their own words, not ``foolproof'' and requires careful tuning of the
circuit parameters to ensure correct and dissipationless operation.

\paragraph{Improvement of adiabatic techniques.}
In 1992 and 1993, a sequence of several important developments proceeded to
solve the remaining difficulties with adiabatic switching.  First, Koller
and Athas {\cite{Koller-Athas-92}} devised a simple and general adiabatic
logic family, but encountered difficulties because their circuits were not
fully logically reversible; Koller and Athas noted that whenever their
circuits finally needed to forget some information, they were unable to
avoid $\sim CV^2$ dissipation, because ultimately, the only way to clear
the logical state of a circuit node whose state is unknown is to tie that
node to a reference reservoir at a known voltage level, thereby dissipating
the energy of the node (if different from the target level).  Being unaware
of Fredkin and Toffoli's earlier work showing that sequential circuits need
never discard information, Koller and Athas did not know any way around
this problem, and went so far as to conjecture (incorrectly) that any
sequential logic circuits (\ie, circuits containing feedback loops) would
require dissipation.

In the meantime, some fully reversible circuit techniques were discovered
independently by nanotechnology enthusiasts Hall
{\cite{Hall-92-v1,Hall-92-v2}} and Merkle
{\cite{Merkle-92,Merkle-93a,Merkle-94}}.  However, Merkle did not discuss
how to implement sequential circuits, and Hall's technique was essentially
non-sequential, and thus algorithmically inefficient.  It required saving
all intermediate results in hardware, using as many clock rails as there
were stages in the computation, then reversing the whole process to recover
energy before beginning the next sequential stage.  In between stages, an
irreversible write of the results of the previous stage was required.

\paragraph{Fully adiabatic CMOS techniques.}
The first adiabatic circuit technique to put together all the key elements
needed for fully universal adiabatic computing was the CRL (``Charge
Recovery Logic'') technique of Younis and Knight, developed in our research
group in 1993 {\cite{Younis-Knight-93}}.  Like the original Fredkin-Toffoli
technique, CRL could implement arbitrary sequential logic.  Like Seitz's
technique, CRL took advantage of an off-chip resonant element.  Like the
Koller-Athas technique, it did not require fine tuning of the circuit
elements.  Putting together these three elements, the Younis-Knight
technique provided the first practically implementable circuit style
capable of reliable, asymptotically reversible operation.

The initial version of CRL was somewhat baroque, but it was later refined
to another version (called SCRL, for ``split-level CRL'') that was
relatively clean and simple
{\cite{Younis-Knight-94,Younis-94,Knight-Younis-95}}.  SCRL was used as the
basis for all of the reversible circuit design work that we will describe
later in this chapter.  In section~{\ref{sec:SCRL}}, we review SCRL in
detail.

\paragraph{Recent adiabatic circuits research.}
Following 1993, there has been a small explosion of literature on and
relating to adiabatic circuits of various types.  The literature has become
too large to review in detail here, but for bibliographical completeness,
we include a sampling of some relevant citations:
{\nocite{Chandrakasan-Brodersen-95}\cite{Athas-etal-94,Denker-etal-94,Kramer-etal-94,Hinman-Schlecht-94,Somasekhar-etal-95,Solomon-Frank-95,Kramer-etal-95,Svensson-95,Tzartzanis-Athas-96,Avery-Jabri-97,Athas-etal-97}}.

\paragraph{Patents on adiabatic circuits}
Additionally, a search for recent patents relating to adiabatic and
reversible computing turned up the following patents from 1995 through
1997:
{\cite{Cezzar-95,Dickinson-96,Frank-96a,Frank-96b,Frank-Solomon-96,Knight-Younis-95,Merkle-94,Ooms-Hallmark-95,Schlecht-Hinman-95,Ye-Roy-96,Thomas-97}.
Most of these patents were assigned to large organizations such as IBM,
MIT, AT\&T, Motorola, and Xerox.  {\ed{Should I review the patents in
detail?}}

\section{A comment on terminology}
\label{sec:adia-rant}

We'd like to pause briefly here for a comment on the term ``adiabatic
circuits'' itself.  Originally in thermodynamics, the word
{\defn{adiabatic}} is an adjective literally meaning ``without flow of
heat'' into or out of the system (\cf\ \cite{SeZeYo84}, \S18-5, p.~352).
So, for example, one way to adiabatically compress a gas would be to
compress it inside an well-insulated chamber so that the heat produced
cannot escape.  Such a compression can be thermodynamically reversible: the
gas can be allowed to adiabatically re-expand, pushing back against the
piston that compressed it while cooling, and the work that was originally
applied to compress the gas can be recovered.

As a result of its frequent usage in such contexts, the term ``adiabatic''
in applied physics has gradually evolved to the point where it is
frequently used to refer not to the lack of heat flow precisely, but rather
to the overall {\emph{thermodynamic reversibility}} (or near-reversibility)
of a process.  Any process that is thermodynamically reversible (at least
in the low-speed limit) has come to acquire the moniker ``adiabatic.''

Note that this new usage is completely orthogonal to the literal meaning of
adiabatic, ``no heat flow.''  A process can involve no heat flow into or out
of the system, yet be thermodynamically irreversible: for example, when a
partition is removed to allow gas originally restricted to one part of a
chamber to expand to fill the whole chamber.  Conversely, a process can
involve heat flow, yet be reversible: for example, if the heat is contained
within an insulated box which is physically moved via a reversible
mechanism out of the region of space identified as ``the system.''

A more accurate term for thermodynamically reversible processes might be
{\emph{isentropic}} (literally, ``with the same entropy''), since
thermodynamically reversible processes are, by definition, those processes
that generate no new entropy.  However, even this term is not precisely
applicable to the circuits referred to as ``adiabatic circuits,'' because
the circuits are not {\emph{perfectly}} isentropic except in the limit of
zero clock frequency and low temperature (to stem the flow of leakage
currents).  The phrase ``{\emph{asymptotically}} isentropic'' would
therefore be a bit more accurate.

However, some of the circuits that have been referred to as ``adiabatic''
are not even {\emph{asymptotically}} isentropic, due to the use of diodes
with a built-in voltage drop.

Essentially, the term ``adiabatic circuit'' is so ill-conceived, and so
polluted with inaccurate and inconsistent usage that we wish that it could
be dropped altogether.  To avoid confusion, we would like to advocate the
adoption of the following alternative, more accurate lexicon:

\begin{itemize}
\item {\defn{energy recovery circuits}} (ER circuits) --- These are
circuits that are designed to recover a substantial portion (but not
necessarily all) of the energy invested in logic signals (\eg\ $CV^2$
static energy).  This could include diode approaches.
\item {\defn{asymptotically isentropic circuits}} (AI\label{p:aicirc} circuits) --- These
are ER circuits that, in some appropriate limit (such as low speed and/or
low temperature) can generate asymptotically zero entropy per operation.
Example: SCRL.
\item {\defn{time-proportionally reversible circuits}} (TPR circuits) ---
AI circuits in which entropy generation per operation is approximately
inversely proportional to the length of time over which operations are
performed.  Example: SCRL when operated in a regime where leakage currents
are small.
\item {\defn{ballistic circuits}} --- Hypothetical TPR circuits in which the
entropy coefficient is so low that the entropy generation per operation is
zero for all practical purposes, even when the circuit is running at its
maximum rate.  Superconducting technologies would probably be required for
this.
\end{itemize}

However, abolishing an established bit of terminology is, in general, a
difficult thing; it confuses people who are accustomed to the old
terminology, and complicates keyword searches for material on a given
topic.  Therefore, despite our academic objections, we bend to popular
usage and continue to use the term ``adiabatic'' when we are referring
generally to circuits of any of the above types.  When we wish to be more
precise than this, we will use one of our more precise terms.

\section{Basic principles of adiabatic circuits}

The core insight behind all adiabatic circuits is that the $\sim CV^2$
minimum dissipation in ordinary switching circuits is due primarily to the
fact that such circuits charge a node by connecting it to a {\emph{constant
voltage}} power supply (\cf\ the discussion in~{\S}\ref{sec:icmosdiss},
p.~\pageref{sec:icmosdiss}).

\paragraph{Constant current sources.}
One alternative means that one might think of for charging up a capacitive
load is to instead use a {\emph{constant current}} power supply, operating
at some appropriate current over some desired length of time.  See
figure~\ref{fig:current}.  One may assume that the charging pathway has
some effective resistance $R$.

We can analyze the dissipation in this case as follows.  Let $C$ be the
load capacitance, $V$ the voltage swing, $R$ the resistance in the charging
pathway, and $t$ the time we wish to take to charge the node.  Then the
charge delivered is $Q=CV$, the current should be $I=Q/t$, and the energy
dissipated in the circuit is

\begin{figure}
\centerline{\psfig{file=current.epsi,width=4in}}
\caption[Charging with constant current]{Charging a node to voltage $V$ via
a constant current over a time $t$.  Compare with fig.~\ref{fig:switch}.
In this case, the dissipation is not $\frac{1}{2}CV^2$, but rather
$CV^2\,\frac{RC}{t}$, which becomes arbitrarily small as the charging time
$t$ is increased.}
\label{fig:current}
\vspace{0.1in}
\hrule
\end{figure}

\begin{eqnarray*}
E_{\rm diss} &=& \int p\,d\tau
= \int i^2R\,d\tau
= I^2Rt
= \left(\frac{Q}{t}\right)^2Rt\\
&=& {\frac{Q^2}{t}}R
= {\frac{(CV)^2}{t}}R
= \fbox{$\displaystyle CV^2\,{\frac{RC}{t}}$}\,.
\end{eqnarray*}

Note that this dissipation scales down proportionally as the charging time
increases.  Therefore this particular charging process is an example of
what we call a {\emph{time-proportionately reversible}} process.

\paragraph{Voltage ramps.}
Can this constant-current procedure be used when charging nodes in a CMOS
logic circuit?  Well, it can at least be closely approximated, by using a
turned-on transistor in place of the resistor, and using a power supply
with a linear voltage ramp in place of the constant current source.  (See
figure~\ref{fig:cmos}.)  An exact analysis of the energy dissipation in
this circuit is more complex, but it can be shown to approach that of the
constant-current circuit very closely when $t\gg RC$.  At the opposite
extreme, when $t\ll RC$, the dissipation approaches that of an ordinary
constant-supply-voltage switching circuit as in~\S\ref{sec:icmosdiss}.  See
fig.~\ref{fig:curves}, and see Younis~\cite{Younis-94} for a more detailed
discussion.

\begin{figure}
\centerline{\psfig{file=cmos.epsi,width=4in}}
\caption[Adiabatic charging in CMOS]{Compare with figure~\ref{fig:current}.
Instead of an ideal current source, we have power supply that provides a
voltage signal $\phi$ that ramps up from 0 to $V$ over a time $t$.  Instead
of an ideal resistor, we have a turned-on CMOS transistor, with gate
voltage biased at some value $V\tg{G} > V+V\tg{T}$ that allows the
transistor to conduct well over the entire voltage range from 0 to $V$,
with an approximate effective resistance of $R$.  For $t\gg RC$,
$E\tg{diss}\approx CV^2 \frac{RC}{t}$; for $t\ll RC$, $E\tg{diss} \approx
\frac{1}{2}CV^2$.}
\label{fig:cmos}
\vspace{0.1in}
\hrule
\end{figure}

\begin{figure}
\centerline{\psfig{file=curves.epsi,width=5in}}
\caption[Voltage curves for slow and fast charging]{Voltage curves for slow
and fast adiabatic charging using a voltage ramp.  If the supply signal
$\phi$ ramps up much faster than the characteristic $RC$ time of the
circuit, then the load voltage $V\tg{L}$ will lag behind the ramp and
approach the supply level in a characteristic exponential-decay curve.
When $\phi$ reaches its peak, the voltage difference across the transistor
is still almost the full swing $V$, leading to the dissipation being almost
$\frac{1}{2}CV^2$.
\setlength{\parindent}{\outerparindent}

On the other hand, if $\phi$ ramps up very slowly, $V\tg{L}$ will track it,
with only a small lag $V\tg{DS}$ that is determined by the rise time, the
transistor's characteristic transconductance $k$, and the drive voltage
$V\tg{dr} = V\tg{G}-V\tg{T}$.}
\label{fig:curves}
\vspace{0.1in}
\hrule
\end{figure}

The same basic technique can also be used to discharge a logic node, with
the supply voltage ramping the other way, from the logic level $V$ back
down to 0.

Note however that these low-dissipation characteristics are only maintained
as long as we charge and discharge all nodes {\emph{only}} using this
technique.  If, on the other hand we ever turn on a transistor when there
is a voltage difference across it, there will be a $\frac{1}{2}CV^2$
dissipation, as in any switching circuit.  So in a fully adiabatic logic
circuit, we need the rule that a transistor can only be turned on if is no
voltage difference across it.  In truly asymptotically isentropic circuits,
this constraint leads to the consequence that logical information cannot be
thrown away---since essentially, in these circuits, the only operation that
throws away information is to dissipatively connect a node to another one
at a different voltage level.

One might object that in this technique we are merely moving the
dissipation from inside the circuit to the power supply which must generate
this swinging logic signal.  But, as we will see later, there are a number
of ways to generate the necessary signal using a {\emph{resonant}} element,
in which circuit energy oscillates back and forth between the on-chip
capacitance and an off-chip inductance.  If the resonant frequency is low
and the off-chip elements have a high quality index, the off-chip elements
need not dissipate significant energy either.

\noheading
The above discussion outlines the basic principles of adiabatic circuits,
but does not get into the details of how build complex logic circuits using
those principles.  There are now a number of different adiabatic logic
techniques available for doing this.  In the next section we review our
technique of choice: SCRL.

\section{The SCRL technique}
\label{sec:SCRL}

As we said earlier, SCRL was the first adiabatic circuit technique to
simultaneously be capable of (1) asymptotically approaching true zero
energy per operation, (2) being integrated on a large scale using standard
CMOS process technology, and (3) operating in pipelined, sequential
fashion.  In this section, we review in detail the operation of SCRL, and
show some new graphical depictions that we find helpful for understanding
its structure and operation.

\subsection{Basic SCRL components}

We start by reviewing the basic elements of which SCRL circuits are
composed.  

Note: The following description breaks down SCRL circuits into functional
elements in a slightly different way than in the original work of Younis
and Knight {\cite{Younis-Knight-94,Younis-94}}.  We find our alternative
decomposition a bit simpler to explain.

In our version, SCRL circuits are separated into two types of components:
(1) clock-driven generalized inverters, and (2) bidirectional latches.

\subsubsection{SCRL clocked generalized inverters}

A clocked SCRL inverter is illustrated in figure~\ref{fig:scrlinv}.  It is
very simple, composed merely of two MOSFET transistors, one n-type and one
p-type.  In fact, it has exactly the same internal structure as an inverter
in ordinary static CMOS (see fig.~\ref{fig:inv} in {\S}\ref{sec:icmos}),
but it is wired and used slightly differently.  Rather than being connected
to constant-voltage supply rails, the FETs are connected to a swinging,
clocked power supply.  The {\nFET} is connected to a clock-supply signal
$\overline{\phi}$ that swings between 0 and $\Vdd/2$---that is, half of the
full signal voltage---with a particular waveform.  The {\pFET} is connected
to a clock $\phi$ that swings between $\Vdd/2$ and $\Vdd$.  We assume
$V\tg{Tn}\approx V\tg{Tp}$, and the voltage swing $\Vdd$ itself is chosen
to be more than twice $V\tg{T}$, so that the transistors will conduct
bi-directionally through the entire swing range of the clocks to which they
are respectively connected.

\begin{figure}
\centerline{\psfig{width=3in,file=scrl-inv.epsi}}\label{p:alogic}
\caption[SCRL inverter]{An SCRL inverter.  It has the same
structure as an ordinary static CMOS inverter (fig.~\ref{fig:inv}a), except
that the supply rails are tied to swinging clock signals rather than to
constant-voltage supplies, and there are various additional assumptions and
constraints on circuit operation.  In between cycles, all nodes are at
$\Vdd/2$.  The input $V\tg{in}$ is assumed to swing to either 0 or {\Vdd}
(representing a logic 0 or 1 as usual) during some period, and for a
shorter period enclosed within this, the clock rails $\phi$ and its logical
inverse $\overline{\phi}$ swing at a constant rate from $\Vdd/2$ to $\Vdd$
and 0, respectively, remain in this state for a time, and then return
smoothly to the neutral level $\Vdd/2$.  (See the timing diagram in the
bottom half of the figure.)  During this time, the output is valid and can
be sampled by a latch (fig.~{\ref{fig:latch}}) to be used in further stages
of processing.  Note that the input must not change while there is a
voltage across either transistor: this is the key property that avoids
$CV^2$ dissipation.  On the right is an icon convenient for representing
this element.}
\label{fig:scrlinv}
\vspace{0.1in}
\hrule
\end{figure}

The operation of the device is as follows.  Initially, all circuit nodes
are at the ``neutral'' level $\Vdd/2$, representing ``no information.''
Being enhancement-mode devices, both transistors are nonconducting at this
time.  Then, the input voltage $V\tg{in}$ swings to a level 0 or $\Vdd$,
representing binary 0 or 1, as in conventional logic.  At this point, one
of the two transistors becomes conducting ({\nFET} on input 1, {\pFET} on
input 0), but no current flows because $\phi = V\tg{out} =
\overline{\phi}$.

Next, the rails $\phi$ and $\overline{\phi}$ swing simultaneously, in a
roughly linear ramp taking some non-infinitesimal rise time $t\tg{r}$, to
their respective extremes.  (They are said to ``split,'', thus the S in
SCRL.)  The output level $V\tg{out}$ will track the rail to which it is
connected.  At this point the output is considered valid, and its value
can, for example, be sampled by a latch (which we will get to in a moment)
for later use.  In the meantime, $V\tg{in}$ must remain (roughly) constant
at its 0 or 1 logic level---this is crucial for preventing dissipation.

At some point after the subsequent stages have finished using the
$V\tg{out}$ signal, the supply rails are brought back together to $\Vdd/2$.
Again, $V\tg{out}$ tracks the rail to which it has remained connected this
whole time.  Then, the input $V\tg{in}$ is free to return to the neutral
level, turning off both transistors again.

Of course, as in ordinary static CMOS, this SCRL inverter structure can be
generalized to compute any $n$-input inverting logic function, such as NAND
or NOR, by simply replacing the {\pFET} and {\nFET} with complementary
networks of {\pFET}s and {\nFET}s, respectively.  (See
figure~\ref{fig:general}.)  The operation of such gates is essentially the
same as that of the simple inverter.  All internal nodes are initially at
$V\tg{dd}/2$, and when the rails are split, all nodes that are connected to
one or the other rail track it, at least up to a threshold drop away from
the extreme point.  (No node can be connected to both rails if the networks
are properly complementary.)  In general, all $n$ inputs must be held
constant during the entire time that the rails are non-neutral.  Then, when
the rails re-merge, all nodes that were pulled away from the neutral level
are gradually pulled back.

\begin{figure}
\centerline{\psfig{file=general.epsi,width=4in}}
\caption[SCRL generalized inverter]{Generalized SCRL inverter.  As in
ordinary static CMOS, the SCRL inverter can be generalized to compute any
inverting logic function $f$ (e.g., NAND, NOR) of $n$ inputs by simply
replacing the single {\pFET} with an arbitrary pull-up network of {\pFET}s,
and the {\nFET} with the complementary network of {\nFET}s.  As in ordinary
CMOS, it is best not to make the logic gates have {\emph{too}} many inputs,
due to the impact on conductance if there are many transistors in series in
the pullup/pulldown network.  Lower conductance decreases speed in static
CMOS, and in SCRL, it also increases the entropy coefficient and the
minimum energy dissipation.  To imitate the conductance of an inverter, the
transistors in a multi-input gate can be made wider, but this of course
consumes more wafer surface area.}
\label{fig:general}
\vspace{0.1in}
\hrule
\end{figure}

A warning: Associated with internal nodes in the pullup/pulldown networks
of a generalized SCRL inverter, there may be a component of dissipation
that does not scale down with frequency.  Fortunately, as we will see
in~\S\ref{sec:scrlsnag}, this problem is easy to fix.

\subsubsection{SCRL bidirectional latches}

Given only generalized SCRL inverters, and no other components, one could
potentially proceed to create combinational logic of any desired depth, by
using a different pair of clock signals for each level of logic, and having
the clocks for earlier stages split before the clocks for the later stages
do, and re-merge after the clocks for the later stages do.  This would be
similar to the ``retractile cascade'' approach of Hall
{\cite{Hall-92-v1,Hall-92-v2}}.  But the problems with this simple approach
are that (1) it would need as many pairs of clock rails as there are stages
in the logic, and (2) the earlier stages must remain idle while the later
stages are computing, and therefore there can be no pipelining, and no
sequential circuits with feedback.

\begin{figure}
\centerline{\psfig{file=latch.epsi,width=4in}}
\caption[SCRL bidirectional latch]{SCRL bidirectional latch.  This special
circuit element, composed of 2 CMOS pass gates with appropriately clocked
controls, is essential for being able to pipeline SCRL logic stages and to
make arbitrary sequential (as opposed to combinational) circuits of any
depth using only a constant number of clock phases.  An icon for the
element is shown on the upper right.}
\setlength{\parindent}{\outerparindent}

Initially, nodes $in\tg{F}$, $in\tg{R}$, and $out$ are all neutral.  The
``forward'' F pass gate turns on, and the ``reverse'' R pass gate turns
off.  Input signal $in\tg{F}$ goes valid with a logic value
A\label{p:alogic2}, driving the output line through gate F.  Before the
input signal goes neutral, gate F closes, so that the output signal will
continue to remain valid after the input goes neutral.  Meanwhile, a later
stage of the computation is reconstructing the value A, and presents it
again on input $in\tg{R}$.  After this happens, gate R opens, tying the
output node to $in\tg{R}$ which is at the same level, so there is no
dissipation.  Then $in\tg{R}$ goes neutral gradually, drawing $out$ back to
the neutral level.  The latch is now ready to process another input on
$in\tg{F}$.

Depending on the relative timing and the presence/absence of overlap of the
$in\tg{F}$ and $in\tg{R}$ signals, the latch may operate in either a
dynamic mode (bottom left), or in a static mode (bottom right).
\label{fig:latch}
\vspace{0.1in}
\hrule
\end{figure}

To solve these problems, SCRL introduces an additional component in between
logic stages, something we call a ``bidirectional latch''
(fig.~\ref{fig:latch}).  Through a ``forward'' pass gate ``F,'' the latch
is adiabatically drawn from its initial neutral level to the logic level
in$\tg{F}$ produced by the preceding logic stage.  The pass gate shuts off,
and then the latch holds its value, allowing the preceding stage to reset
and prepare to accept a new input, while in the meantime the succeeding
logic stage uses the value held on the latch as its own input for further
computations.  But after the succeeding logic stage finishes, there is a
small problem: How do we clear the latch to accept a new input from the
preceding stage?  We cannot just dump the latch to a constant voltage
because that would be irreversible and dissipative.  Instead, the latch
must be discharged adiabatically by a controlling component that knows what
level to discharge it from.  The {\emph{preceding}} logic stage no longer
knows what value the latch is holding, because it has already gone on to
reset itself and process new data (allowing this was the whole point of the
latch).  However, the key insight is that the {\emph{succeeding}} logic
stage now contains information that depends on the latched value.  If that
succeeding logic stage has computed some {\emph{invertible}} function of
its inputs, then the value in the latch can be reconstructed based on the
information that the succeeding stage has calculated, and using this
knowledge, the latch can be reversibly cleared.

To provide this adiabatic ``unwriting'' functionality, the latch provides a
second write port, in the form of a second ``reverse'' pass gate ``R''.
Logic in the succeeding stage presents a reconstructed copy of the latched
value on input in$\tg{R}$, then the reverse pass gate opens, and is drawn
back to the neutral level through pass gate R.  Also, the latch provides a
second ``read port'' in the form of a wire of the output node leading back
to the preceding stage, which uses this input to reconstruct and clear the
values stored in the preceding level of latches.

Two different alternative timing disciplines for these latches are shown in
the bottom half of fig.~\ref{fig:latch}.  Note that the pass gates are
turned off and on adiabatically by gradually-swinging ramps, and that they
are never turned on when there is a voltage across them.

\subsection{SCRL pipelines}

Putting it all together, figure~\ref{fig:pipe} shows the structure of a
complete SCRL pipeline.  The arrows in this figure represent many parallel
wires, each function block represents a parallel set of logic gates all
using the same clock, and each bidirectional-latch icon represents a
parallel set of bidirectional latches, all on the same clock.  The
direction of the arrows shows the direction of information flow.  As you
can see, each set of ``forward'' logic gates that computes a logic function
is paired with a corresponding set of gates, pointing the other way, which
is used to uncompute the latched values from the previous logic stage.
Each forward or reverse stage, and each latch, operates on a different set
of clock signals.  However, after some small number of stages, the earlier
clock signals may be used again.  This allows arbitrary sequential circuits
with feedback loops (such as CPUs) to be constructed.

\begin{figure}
\centerline{\psfig{file=pipe.epsi,width=4in}}
\caption[SCRL pipeline]{SCRL pipeline.  A pipeline of arbitrary sequential
logic in SCRL can be constructed by chaining together generalized inverters
and bidirectional latching in the following way.  A parallel set of
generalized inverters is grouped together into a multi-input, multi-output
function $f_1$ which must be {\emph{invertible}}, and this block is paired
with a corresponding block that computes the inverse function $f^{-1}$.
The two blocks are powered by two clock phases $\phi\tg{1F}$ and
$\phi\tg{1R}$ that are offset relative to each other.  Then comes a
bidirectional latch $P_1$ and another pair of functional blocks.
\setlength{\parindent}{\outerparindent}

The basic operational cycle is that $f_1$ computes and its output $X_1$ is
latched onto $P_1$.  Then $f_2$ computes and its output $X_2$ is latched
onto $P_2$, then $f_2^{-1}$ computes $X_1$ from $X_2$, and ``unlatches''
$P_1$ back to the neutral level.  Now $f_1$ can process a new input and
store the result $Y_1$ on $P_1$, at the same time that a further stage
$f_3$ is using the value computed from the earlier value $X_1$.  In this
way, waves of information propagate down the pipeline as they are being
processed.  The pipeline can even loop back on itself, as long as phases
are matched properly.  If the clock timing is inverted, information flows
in the opposite direction.

The bottom part of the figure illustrates how non-inverting logic functions
can be computed in a single SCRL stage by the use of a second intermediate
level of logic.  The second level uses a clock whose active period is
enclosed within that of the first level's clock, like a 2-level version of
one of Hall's retractile cascades.  With 2 levels per stage in an SCRL
pipeline, one can do universal reversible sequential logic.}
\label{fig:pipe}
\vspace{0.1in}
\hrule
\end{figure}

Normally, each logic stage can only compute an inverting function, and so
there is a potential difficulty that if one initially has a value but not
its complement, one cannot, in a single later stage, have access both to
the value and its complement.  This difficulty can be fixed by having a
2-level retractile cascade within each stage of logic, as illustrated in
the bottom part of fig.~\ref{fig:pipe}.  An alternative way to fix the
problem would be to maintain a dual-rail signaling discipline, with
complements of every logic value always available, but this would in
general require more area.

\subsection{Timing disciplines}

There are a variety of alternative timing disciplines in SCRL.  These vary
in terms of the number of clock phases, and whether they are dynamic or
fully static.  The simplest fully-static discipline is 3-phase; the timing
diagram for this is illustrated in fig.~\ref{fig:timing}.  If one wishes to
permit dynamic operation (floating nodes), 2 phases will suffice.  

\begin{figure}
\psfig{file=timing.epsi,width=\textwidth}
\caption[Full SCRL timing diagram]{Full timing diagram for 3-phase,
non-inverting, static SCRL.  This was the timing discipline used in our
designs.  On the right is a vertical representation of a sequence of 3
pipeline stages, using a slightly different notation from that presented in
figs.~\ref{fig:scrlinv}--\ref{fig:latch}: the squares are bidirectional
latches, and the triangles are generalized SCRL inverters.  Each element's
clock is shown exactly to its left on the timing diagram.  Time goes from
left to right on the timing diagram, and information flows from top to
bottom in the pipeline.  This scheme requires 16 clock signals and their
inverses, and 24 distinct non-overlapping transition steps per complete
clock period.  The shaded regions indicate times when valid logic values
are present on the various latches.}
\label{fig:timing}
\vspace{0.1in}
\hrule
\end{figure}

We used 3-phase SCRL in our designs, because when running at very slow
clock speeds, dynamic circuits would have been vulnerable to incorrect
functionality, because (at normal temperatures) the charge stored
capacitively on a dynamic node may leak out over long periods.  With fully
static circuits, we could be more confident that functionality would remain
correct even when running at the very slow speeds that minimize energy
dissipation, speeds at which the switching currents become nearly as small
as the leakage currents.

For more detailed descriptions of the various timing disciplines see Younis
1994 {\cite{Younis-94}}.

\section{SCRL circuit analyses}
\label{sec:scrl-anal}

In this section, we carry through a variety of CMOS circuit analyses in
order to better understand interesting aspects of SCRL's scaling behavior.
First, {\S}\ref{sec:scrlmodel} presents a simplified model of SCRL that we
will use in our analyses.  Then in~\S\ref{sec:scrldiss}, we derive an
expression for the switching energy dissipation in SCRL in any given
technology, in terms of raw characteristics of the technology, such as the
threshold voltages and transconductance parameters of its transistors.
In~\S\ref{sec:minenerg}, we extend this by taking leakage currents into
account, and derive analytical expressions showing how to adjust speed and
threshold voltage to minimize total dissipation in SCRL at a given
temperature.  Those analyses are based on a fairly simple model of CMOS
transistors, which becomes somewhat inaccurate in very small devices.

Following this, section~\ref{sec:scrlsnag} reveals a case in ordinary SCRL
where the dissipation seems to be larger than in the ideal model, and shows
a way to fix it.  Then later, in~\S\ref{sec:scrlscale}, we will talk about
some of the long-term limits involved in scaling CMOS and SCRL technology
to smaller length scales.

\subsection{A simple SCRL model for analysis}
\label{sec:scrlmodel}

Switching energy is dissipated in an SCRL circuit whenever the voltages on
some logic gate's power supply rails $\phi, \overline{\phi}$ change.
Energy is dissipated within the transistors of the gate's pullup/pulldown
networks, and also in the transistors of the transmission gate in the
bidirectional latch attached to the gate's output.  However, to simplify
the analysis, we will lump together all the turned-on transistors within
which dissipation occurs during a transition, and treat them as if they
were a single transistor, as in figure {\ref{fig:model}}.

\begin{figure}
\centerline{\psfig{width=2.6in,file=modelv3.epsi}}
\caption[Simplified SCRL circuit model]{Simplified circuit model for SCRL analysis.  Compare with
figs.~\ref{fig:scrlinv} (p.~\pageref{fig:scrlinv}) through
{\ref{fig:latch}} (p.~\pageref{fig:latch}).  In the simple model, we only
look at a single transition, and we use a single transistor to represent
the path through an arbitrary pulldown network and a transmission gate in a
latch.}
\label{fig:model}
\vspace{0.1in}
\hrule
\end{figure}

We can consider a number of different cases for switching.  A gate's
output node voltage may be switched either through the gate's pulldown
network of {\nFET}s or through its pullup network of {\pFET}s.  And the
switching activity may either be to clear the output or to set the
output.  When an output node is cleared, its voltage goes from a valid
level (0 or $V_{\rm dd}$) to the neutral value $V_{\rm dd}/2$; when it
is set, its value goes from $V_{\rm dd}/2$ to 0 or $V_{\rm dd}$.

However, all these cases are symmetrically similar to each other with
regards to how their energy dissipation scales with speed, threshold
voltage, and temperature.  Therefore, rather than analyzing them all
separately, we will just consider one case: where the voltage $V_{\rm
L}$ on the load capacitance $C_{\rm L}$ on the output node is charged
up from 0V to $V_{\rm dd}/2$, through a turned-on {\nFET} which
represents the gate's pull-down network and N pass transistor.

In our analysis, we will ignore any dissipation that occurs during
switching in transistors along paths that do not actually connect all the
way through to the gate's output.  For example, we ignore energy
dissipation that occurs when switching with the transmission gate turned
off.  As another example, referring forward to the NAND gate in figure
{\ref{fig:scrlfix}} (p.~\pageref{fig:scrlfix}), we can see that if input A
is high and input B is low, then transistor T3 will be turned on, and so
there will be some dissipation through it, even though it does not connect
through to the output.  Ignoring such dissipations is a simplification that
is fairly well justified, because these dissipations involve driving
relatively small capacitances compared to the external load.  In adiabatic
charging, there is a quadratic dependence of dissipation on the capacitance
being driven.  So the total dissipation we are ignoring should not be
large, compared to the dissipation that we are including.

We assume that the {\pFET}s and {\nFET}s in the SCRL circuit have been
sized so that their gain factors are equal, $k_{\rm n} = k_{\rm p} = k$
(matching the rise/fall delay times), and we assume that the {\pFET} and
{\nFET} threshold voltages are also equal, $V_{\rm t0n} = V_{\rm t0p} =
V_{\rm t0}$, so that the analysis of the dissipation through the pulldown
network comes out the same for the pullup network.

\subsection{Switching losses as a function of technology parameters}
\label{sec:scrldiss}

To determine the energy dissipation of our model circuit
(fig.~\ref{fig:model}), we would like to know the voltage on the load at
each moment during the transition, $V_{\rm L}(t)$, because this would tell
us the instantaneous drain-to-source voltage $V_{\rm DS}(t)$ across the
transistor, which we could plug into the device's current-voltage relation
to give us the instantaneous current $I(t)$, and thence the instantaneous
power, which we could integrate over time to find the total energy
dissipation of the transition $E_{\rm tr}$:
\begin{eqnarray}
E_{\rm tr} & = & \int_{t=0}^\infty P(t) dt \\
       & = & \int_{t=0}^\infty I(t) V_{\rm DS}(t) dt \label{eq:int}
\end{eqnarray}

Unfortunately, $V_{\rm L}(t)$ itself is determined by integrating the
current $I(t)$ flowing into the load capacitance $C_{\rm L}$, so that
determining closed-form formulas for $I(t)$ and $V_{\rm DS}(t)$ requires
solving a tricky differential equation, which we will not attempt here.
Instead, we will approximate the energy dissipation by treating the
limiting case where the supply rise time $t_{\rm r}$ is very large compared
to the characteristic $RC$ time constant of the circuit, where $R$ is the
effective resistance of the turned-on transistor.  Cases where the rise
time is comparable to $RC$ will not be adequately addressed by the below
analysis.

To understand this limiting case, refer back to the diagrams in figure
{\ref{fig:curves}} (p.~\pageref{fig:curves}).  Diagram (a) shows
qualitatively what would happen if the supply rail were to rise very
quickly compared to $RC$.  Essentially the output voltage would rise at an
exponentially-decaying rate and asymptotically approach the supply voltage,
just as happens in a regular CMOS inverter whose input switches very
quickly.  The energy dissipation $E_{\rm fast}$ for this fast-switching
case is well known to be, as in~\S\ref{sec:icmosdiss},
p.~\pageref{sec:icmosdiss},
\begin{equation}
E_{\rm fast} = {\frac{1}{ 2}}C_{\rm L}(\Delta V)^2,\label{eq:cv2}
\end{equation}
which in our case is (with $\Delta V = V_{\rm dd}/2$)
\begin{equation}
E_{\rm fast} = {\frac{1}{ 8}}C_{\rm L} V_{\rm dd}^2.\label{eq:fast}
\end{equation}

On the other hand, figure \ref{fig:curves}(b) shows what happens in
the case which we will now analyze, where the supply rail rises very
slowly.  The output voltage $V_{\rm L}$ will initially rise slowly,
but as the voltage drop $V_{\rm DS}$ across the transistor increases,
the current $I(t)$ through the transistor will also rise, until an
equilibrium is reached at which point $V_{\rm L}$ is rising at the
same rate as the input voltage, but lagging behind it by a small
amount $V_{\rm DS} = IR$.  Then, when the input voltage stops rising,
the output voltage will finish the approach to $V_{\rm dd}/2$ in
asymptotic fashion, with an $RC$ time constant.

We note that if the input rises slowly, $V_{\rm DS}$ is always small
compared to $V_{\rm dd}/2$, and so $V_{\rm L}(t) \approx \phi(t)$.
During the transition, $d\phi/dt$ is constant, and so the current $I =
C_{\rm L} {\frac{dV_{\rm L}}{ dt}}$ through the transistor will be
approximately constant as well.  $I$ will be the quotient of the total
charge $Q = C_{\rm L} V_{\rm dd}/2$ that is transfered to the load
capacitance, divided by the supply rail rise time $t_{\rm r}$, since
that is the time during which almost all of this charge is transfered.
\begin{equation}
I(t) \approx I = Q/t_{\rm r} = {\frac{C_{\rm L} V_{\rm dd}/2}{ t_{\rm r}}}
\label{eq:i}
\end{equation}

Now, armed with this constant current $I$, we can use the standard MOSFET
triode-regime current-voltage formula (\cf\ {\cite{Rabaey96}}, \S2.3.2,
p.~44, eq.~2.47) to derive a closed form expression for $V_{\rm DS}$.  The
reason we use the triode-regime rather than the saturation-regime formula
is that turned-on transistors in SCRL are never in
saturation.\footnote{This formula may not be appropriate for turned-on
transistors if $V_{\rm dd}$ is about as small as the thermal voltage
$\Vth=\kT/\ech$, since then even turned-on transistors may only be in
moderate or weak inversion, and the current may scale exponentially with
$V_{\rm GS}$ rather than according to the triode formula.  This is one area
where the present analysis needs refinement.}

In the following, $V_{\rm GS}$ is the gate-to-source voltage, and
$V_{\rm T}$ the threshold voltage.  Everything except $k$ (the
transistor's gain factor) is here implicitly a function of $t$.
\begin{equation}
I = k\left((V_{\rm GS}-V_{\rm T})V_{\rm DS} - {\frac{V_{\rm
DS}^2}{2}}\right)
\label{eq:sqlaw}
\end{equation}
Let's write $V_{\rm GS}-V_{\rm T}$ as $V_{\rm dr}$ (drive voltage) for conciseness.
\begin{equation}
I = k\left(V_{\rm dr} V_{\rm DS} - {\frac{V_{\rm DS}^2}{2}}\right)
\end{equation}
We can easily solve this equation for $V_{\rm DS}$, using the quadratic formula.
\begin{eqnarray}
&&{\frac{I}{k}} = V_{\rm dr} V_{\rm DS} - {\frac{V_{\rm DS}^2}{2}} \\
&&{\frac{1}{2}}V_{\rm DS}^2 - V_{\rm dr} V_{\rm DS} + {\frac{I}{k}} = 0
\end{eqnarray}
\begin{eqnarray}
V_{\rm DS} &=& {\frac{V_{\rm dr} \pm \sqrt{(-V_{\rm dr})^2 - 4\left({\frac{1}{
2}}\right)\left({\frac{I}{ k}}\right)} }{ 2\left({\frac{1}{ 2}}\right)}}
\nonumber \\
\\
           &=& V_{\rm dr} - \sqrt{V_{\rm dr}^2-2{\frac{I}{ k}}} \label{eq:vds}
\end{eqnarray}

Now, let us make a further simplification of eq.~\ref{eq:vds}.  We
observe that our earlier approximation, that $I(t)$ was constant,
assumed that $t_{\rm r}$ is large, and therefore that $I$ is small
(from eq.~\ref{eq:i}).  With $I\ll kV_{\rm dr}^2$, this will allow us
to approximate eq.~\ref{eq:vds} as follows.  We observe that $V_{\rm
DS}$ will be approximately linear in $I$ for these small $I$s.
$V_{\rm DS}$ will pass through 0 at $I=0$, and the slope is given by
$dV_{\rm DS}/dI$:
\begin{eqnarray}
{\frac{dV_{\rm DS}}{ dI}} 
  &=& {\frac{d}{ dI}}\left(V_{\rm dr} - \sqrt{V_{\rm dr}^2-2{\frac{I}{ k}}}\right) \\
  &=& -{\frac{1}{ 2}}\left(V_{\rm dr}^2-2{\frac{I}{ k}}\right)^{-{\frac{1}{2}}}\left({\frac{-2}{ k}}\right) \nonumber \\
\\
  &=& {\frac{1}{ k\sqrt{V_{\rm dr}^2-2{\frac{I}{ k}}}}} \\
  &\approx& {\frac{1}{ k\sqrt{V_{\rm dr}^2}}} {\ \ \text{(for\ small\ {\em I})}} \\
  &=& {\frac{1}{ kV_{\rm dr}}}.
\end{eqnarray}
Given this slope, and the fact that $V_{\rm DS}=0$ when $I=0$, we can
therefore simplify eq.~\ref{eq:vds} to the very concise form
\begin{equation}
V_{\rm DS} \approx I/kV_{\rm dr}.\label{eq:vds2}
\end{equation}

Now, the drive voltage $V_{\rm dr}$ is itself actually time-dependent,
because it is defined in terms of the gate-to-source voltage $V_{\rm
GS}$, and although the gate voltage is constant, the transistor source
voltage changes linearly over time $t_{\rm r}$, from 0 to $V_{\rm
dd}/2$, following $\phi(t)$.
\begin{eqnarray}
V_{\rm dr}(t) & \equiv & V_{\rm GS}(t) - V_{\rm T}(t) \\
              & = & \left[V_{\rm G} - V_{\rm S}(t)\right] - V_{\rm T}(t) \\
              & = & \left(V_{\rm dd} - {\frac{V_{\rm dd}}{ 2}}{\frac{t}{ t_{\rm r}}}\right) - V_{\rm T}(t) \nonumber \\
\\
	      & = & \left(V_{\rm dd} - V_{\rm T}(t)\right) - {\frac{V_{\rm dd}}{ 2}}{\frac{t}{ t_{\rm r}}}
\end{eqnarray}
Moreover, $V_{\rm T}(t)$ as well will vary along with the supply
voltage, due to the changing body effect as the source voltage
changes.  For example, when the supply voltage is at $V_{\rm dd}/2$,
$V_{\rm T}$ might be perhaps (as a roughly estimated typical value)
50\% above the minimum value $V_{\rm T0}$ that it has when $\phi=0V$.
Using the correct formulas for $V_{\rm GS}$ and $V_{\rm T}$, the
energy integral in equation
\ref{eq:int} would still a bit too complicated to conveniently
evaluate, although if we really cared to do it, we could.

But instead, let's just make the rough approximation that $V_{\rm
dr}(t)$ is constant, and is equal to
\begin{equation}
V_{\rm dr} = {\frac{3}{ 4}}V_{\rm dd} - b_{\rm avg} V_{\rm T0},\label{eq:vdr}
\end{equation}
taking the average of the initial ($V_{\rm dd}$) and final ($V_{\rm
dd}/2$) values of $V_{\rm GS}(t)$, with an average body-effect factor
$b_{\rm avg} = V_{\rm T}/V_{\rm T0}$ for a typical body-effected
$V_{\rm T}$.  The reason for expressing the body-effected threshold
$V_{\rm T}$ as a multiple of $V_{\rm T0}$ is that it will later allow
us to derive a very simple expression for the switching energy.

Now, with our approximate constant expressions for $I$
(eq.~\ref{eq:i}) and $V_{\rm dr}$ (eq.~\ref{eq:vdr}), we can consider
$V_{\rm DS}$ as given by eq.~\ref{eq:vds2} to be roughly constant,
which allows us finally to approximate the transition energy integral
(eq.~\ref{eq:int}) and derive a fairly simple expression for $E_{\rm
tr}$ in the slow-transition limiting case.  We set the upper bound on
the integral to be time $t_{\rm r}$ rather than $\infty$, in
observance of the fact that in the slow-transition limit, most of the
energy dissipation occurs by time $t_{\rm r}$.
\begin{eqnarray}
E_{\rm tr} &\approx& \int_{t=0}^{t_{\rm r}} I(t) V_{\rm DS}(t) dt \\
       &\approx& I V_{\rm DS} t_{\rm r} \\
       &=& I \left({\frac{I}{kV_{\rm dr}}}\right) t_{\rm r} \\
       &=& {\frac{I^2 t_{\rm r} }{ k V_{\rm dr}}} \\
       &=& {\frac{\left(\frac{C\tg{L} \Vdd/2}{t\tg{r}}\right)^2 t_{\rm r}}{ k V_{\rm dr}}} \\
       &=& {\frac{C_{\rm L}^2 V_{\rm dd}^2 }{ 4 t_{\rm r} k V_{\rm dr}}} \label{eq:etr}
\end{eqnarray}

Now, we would like to take another simplifying step, by assuming that
our maximum power supply voltage $V_{\rm dd}$ is being scaled
proportionately to $V_{\rm T0}$, and is equal to
\begin{equation}
V_{\rm dd} = n_{\rm dd} V_{\rm T0} \label{eq:vdd}
\end{equation}
where $n_{\rm dd}$ indicates the scaling factor used for determining
$V_{\rm dd}/V_{\rm T0}$.  SCRL will not work properly if $V_{\rm dd}$
is too close to the threshold voltage $V_{\rm T0}$.  A reasonable
value for $n_{\rm dd}$ for SCRL might be 4.  Anyway, given
eqs.~\ref{eq:vdd} and \ref{eq:vdr}, we can substitute $V_{\rm dd}$ and
$V_{\rm dr}$ in eq.~\ref{eq:etr} to re-express it in terms of a single
voltage parameter $V_{\rm T0}$, the zero-bias threshold voltage:
\begin{eqnarray}
E_{\rm tr} &=& {\frac{C_{\rm L}^2 (n_{\rm dd} V_{\rm T0})^2 }{ 4 t_{\rm r} k \left({\frac{3}{ 4}}n_{\rm dd} V_{\rm T0} - b_{\rm avg} V_{\rm T0}\right)}} \\
       &=& {\frac{C_{\rm L}^2 n_{\rm dd}^2 V_{\rm T0}^2 }{ 4 t_{\rm r} k \left({\frac{3}{ 4}}n_{\rm dd} - b_{\rm avg}\right) V_{\rm T0}}} \\
       &=& \left(\frac{n_{\rm dd}^2}{ 3 n_{\rm dd} - 4b_{\rm avg}}\right)
		 {\frac{C_{\rm L}^2 V_{\rm T0} }{ t_{\rm r} k}},\label{eq:etrbig}
\end{eqnarray}
and let us finally just make this a bit more concise by renaming the
factor containing $n_{\rm dd}$ as just
\begin{equation}
c_{\rm dd} \equiv n_{\rm dd}^2/(3n_{\rm dd}-4b_{\rm avg}).
\end{equation}
To illustrate what a typical value of $c_{\rm dd}$ might be, if $n_{\rm
dd}=4$ and $b_{\rm avg}=1.25$ ({\it i.e.}, average body-effected threshold
25{\pct} above $V_{\rm T0}$), then $c_{\rm dd}\approx1.45$.

Anyway, we can now write the transition energy formula
(\ref{eq:etrbig}) as just
\begin{equation}
\fbox{
  \begin{minipage}{1.2in}
  \vspace{-\abovedisplayskip}
  $$E_{\rm tr} = c_{\rm dd} {\frac{C_{\rm L}^2 V_{\rm T0} }{ t_{\rm r}k}}.$$
  \end{minipage}
} \label{eq:etr2}
\end{equation}

There are a couple of very interesting things to note about equation
\ref{eq:etr2}, when compared to equations like eq.~\ref{eq:cv2}
that govern the dissipation in fast SCRL transitions or ordinary CMOS
transitions.

The first thing is that the transition energy in eq.~\ref{eq:etr2}
scales in proportion to the square of the load capacitance, in
contrast to traditional CMOS where the $CV^2$ dissipation scales only
linearly with capacitance.  The reason is that higher capacitance
means higher currents through our transistors, and thus a larger
voltage drop across them, in addition to greater charge to move across
that drop.  So in designing SCRL circuits we must be even more careful
to get load capacitances small than we are in regular CMOS.  Unless
most of the capacitance is in the interconnects, minimum-sized
transistors are favored.  If most capacitance is in transistor gates
and PN junctions, then increasing transistor widths increases energy
dissipation roughly linearly (not quadratically, because $k$ is scaled
too).  The flip side of this coin is that SCRL benefits greatly from
improved process technologies that allow smaller, less capacitive
transistors.

The other very interesting point is that given a constant $n_{\rm dd}$
ratio between supply and threshold voltages, and everything else but
$V_{\rm T0}$ also constant, the switching energy of SCRL circuits {\em
decreases only linearly with decreasing threshold voltage}, in
contrast to the quadratic drop of traditional CMOS due to its $CV^2$
switching energy.  Intuitively, the reason is because as voltages go
down in SCRL, the effective on-resistance of our transistors
increases, so the voltage drop across the transistors during
transitions is increased, causing higher dissipation.  In standard
CMOS, the voltage drop across the transistors during switching is
already as high as possible, and so making them more resistive doesn't
affect the dissipation at all.

Equation \ref{eq:etr2} is interesting and useful on its own, because
it allows us to predict the switching energy of SCRL circuits
constructed in particular process technologies, and helps guide us in
designing these circuits.  But now, let's go a little further, and use
eq.~\ref{eq:etr2} as part of a more sophisticated analysis of SCRL
energy dissipation that includes the effects of leakage.

\subsection{Minimizing the sum of switching and leakage energy}
\label{sec:minenerg}

In this section we explore how to minimize the energy dissipation of SCRL
when taking leakage into account.  First, in~\S\ref{sec:adjspeed} we see
how to minimize energy dissipation when the speed of operation is
adjustable but all other technology parameters are held fixed.  Then,
in~\S\ref{sec:adjvolt} we will see how to minimize dissipation when the
choice of device threshold voltage (and supply voltage) is also adjustable,
but other parameters such as device geometry and operating temperature are
fixed.

\subsubsection{Adjusting speed to minimize dissipation}
\label{sec:adjspeed}

One often-cited characteristic of the switching energy of adiabatic
circuits, based on equations like eq.~\ref{eq:etr2}, is that it decreases
linearly with increasing transition time $t_{\rm r}$, leading to the
conclusion that the energy per operation of SCRL circuits can be made
arbitrarily small by just making the transition time larger.  However,
given current device technologies, this statement is somewhat misleading,
because MOS transistors also have a leakage power dissipation that is
always present, and thus contributes a term to total energy per operation
that increases linearly with increasing time per operation.  This means
that there is some speed at which the energy per operation of an SCRL
circuit is minimized; at faster speeds, the switching energy dominates, and
at lower speeds, the leakage energy dominates.  In this section we derive a
formula for the optimal rise time for minimizing total energy per
operation.

Let us consider what happens to a signal wire in an SCRL circuit during a
complete cycle, from the time it first holds one valid value to the time it
first holds the next.  During this time there will be two complete
transitions on the wire: one from the old value to $V_{\rm dd}/2$, the
other from $V_{\rm dd}/2$ to the new value.  The total time for the
complete cycle depends on the number of phases in the particular SCRL
clocking discipline in question.  A complete cycle of the 2-phase SCRL
described by Younis {\cite{Younis-94}} is the length of 18 transitions;
3-phase and 4-phase SCRL take 24 transitions (\cf\ fig.~\ref{fig:timing},
p.~\pageref{fig:timing}), etc.  These numbers are probably not minimal.
Anyway, let $n_{\rm t}$ be the number of transitions per cycle; the total
cycle time is then $T = n_{\rm t} t_{\rm r}$.

Now we can write down an expression for the total energy dissipation
associated with this signal wire per complete cycle, including terms
for both the transition energy and the leakage energy, where the
leakage energy is expressed in terms of $P_{\rm leak}$, the average
leakage power associated with the signal wire:
\begin{eqnarray}
E_{\rm tot} &=& 2E_{\rm tr} + P_{\rm leak} T\\
        &=& 2 c_{\rm dd} {\frac{C_{\rm L}^2 V_{\rm T0} }{ t_{\rm r} k}} + P_{\rm leak} n_{\rm t} t_{\rm r}.
	\label{eq:etot}
\end{eqnarray}
where the multiplication by 2 comes from the above-mentioned fact that
an SCRL wire undergoes two transitions per cycle.

We want to find the $t_{\rm r}$ that minimizes $E_{\rm tot}$.  First,
let us collapse everything except $t_{\rm r}$ into coefficients $a$\label{p:acoeff}
and $b$:
\begin{eqnarray}
a &\equiv& 2 c_{\rm dd} C_{\rm L}^2 V_{\rm T0} / k \\
b &\equiv& P_{\rm leak} n_{\rm t} \\
E_{\rm tot} &=& {\frac{a }{ t_{\rm r}}} + b t_{\rm r}. \label{eq:etot2}
\end{eqnarray}

Figure~\ref{fig:evstr} shows how the total energy in eq.~\ref{eq:etot2}
scales with $t_{\rm r}$, regardless of the values of $a$ and $b$.  We can
see that at very high values of $t_{\rm r}$, $E_{\rm tot}$ is high because
of the high leakage energy, and at very low values of $t_{\rm r}$, $E_{\rm
tot}$ is high because of the high switching energy.  In between, there is a
point where the total energy is minimized.

\begin{figure}
\centerline{\psfig{width=3in,file=evstr.epsi}}
\caption[Scaling of energy/op in SCRL with speed, given nonzero
leakage]{How total energy dissipation per operation scales with ramp rise
time $t_{\rm r}$ in SCRL, when leakage is significant.  The increasing line
is leakage energy, the inversely declining curve is switching energy.
Their sum is analytically proven to be minimized when the two components
are equal.}
\label{fig:evstr}
\vspace{0.1in}
\hrule
\end{figure}

We can find a formula for the $t_{\rm r}$ at this point; it's just
where the derivative of eq.~\ref{eq:etot2} equals zero, which turns
out to be where the switching energy equals the leakage energy:
\begin{equation}
 {\frac{d}{ dt_{\rm r}}}\left({\frac{a }{ t_{\rm r}}} + b t_{\rm r}\right) = 0
\end{equation}
\begin{equation}
 -{\frac{a }{ t_{\rm r}^2}} + b = 0
\end{equation}
\begin{equation}
 t_{\rm r} = \sqrt{\frac{a }{ b}} 
  = \sqrt{\frac{2 c_{\rm dd} C_{\rm L}^2 V_{\rm T0} }{ k P_{\rm leak} n_{\rm t}}}
\end{equation}
\begin{equation}
\fbox{
  \begin{minipage}{2.2in}
    \vspace{-\abovedisplayskip}
    $$t_{\rm r} = \sqrt{\frac{2 c_{\rm dd} }{ n_{\rm t}}} \cdot
                C_{\rm L} \sqrt{\frac{V_{\rm T0} }{ k P_{\rm leak}}}$$
  \end{minipage}
} \label{eq:tr}
\end{equation}

At this minimum-energy setting for $t_{\rm r}$, the total energy
dissipation is:
\begin{eqnarray}
E_{\rm tot} &=& {\frac{a }{ t_{\rm r}}} + b t_{\rm r} \\
E_{\rm min} &=& {\frac{a }{ \sqrt{a/b}}} + b \sqrt{a/b} \\
	&=& \sqrt{\frac{a^2}{ a/b}} + \sqrt{b^2 a / b} \\
	&=& \sqrt{ab} + \sqrt{ab} \text{\ \ \ (note identical terms)}\\
	&=& 2\sqrt{ab} \\
	&=& 2\sqrt{{\frac{2 c_{\rm dd} C_{\rm L}^2 V_{\rm T0} }{ k}} P_{\rm leak} n_{\rm t}}
\end{eqnarray}
\begin{equation}
\fbox{
  \begin{minipage}{2.6in}
    \vspace{-\abovedisplayskip}
    $$E_{\rm min} = \left(2\sqrt{2 c_{\rm dd} n_{\rm t}}\right) C_{\rm L}
     \sqrt{\frac{V_{\rm T0} P_{\rm leak}}{ k}}$$
  \end{minipage}
} \label{eq:emin}
\end{equation}

Looking at eq.~\ref{eq:emin}, if we want the energy per operation of
an SCRL circuit to be as low as possible, we will want to first
minimize the wiring capacitance and other parasitic capacitances we
need to drive.  Then we'd want to maximize the gain factor $k$ of our
transistors.  However, if we try to increase $k$ by making the
transistors wider, this also increases the capacitance, and the
leakage power.  So narrower transistors are favored.

Ideally we'd like to get a handle on minimum energy by adjusting the
threshold voltage, so as to minimize the quantity $V_{\rm T0} P_{\rm
leak}$ in eq.~\ref{eq:emin}.  But choosing the optimal $V_{\rm T0}$ is
actually a bit tricky, since $P_{\rm leak}$ itself depends on $V_{\rm
T0}$, in a way which we will now analyze.

\subsubsection{Adjusting voltages to minimize dissipation}
\label{sec:adjvolt}

In a single transistor across which there is a voltage drop of $V_{\rm
DS} = V_{\rm dd}$, which we will later see suffices to model the
leakage through all the transistors attached to a given SCRL signal
wire, the leakage power $P_{\rm leak}$ is given by
\begin{eqnarray}
P_{\rm leak} &=& I_{\rm leak} V_{\rm dd} \\
         &=& I_{\rm leak} n_{\rm dd} V_{\rm T0}\label{eq:pleak}
\end{eqnarray}
and $I_{\rm leak}$ for transistors that are supposed to be ``off''
($V_{\rm GS} \leq V_{\rm T}$) is given by a standard formula
\begin{equation}
I_{\rm leak} = I_0 e^{(V_{\rm GS}-V_{\rm T})/((1+\alpha)k_{\rm B}T/q)}
\label{eq:ileak}
\end{equation}
where $I_0$ denotes the leakage current when the transistor is just barely
on the edge of being off ({\it i.e.}, when $V_{\rm GS} = V_{\rm T}$).
$k_{\rm B}$ is Boltzmann's constant, $T$ is the absolute temperature, $q$
is the magnitude of the electron charge, and $\alpha$ is a
technology-dependent constant fudge factor, which is ideally 0 but in
practice is perhaps closer to 1.  This factor is needed because real
devices are found empirically to have a greater dependence of leakage on
temperature than is predicted by the theoretical ideal.

Now, the leakage in SCRL circuits is not really continuous, but
fluctuates during the SCRL cycle as different rails split and merge.
In static versions of SCRL such as Younis's 3-phase clocking scheme,
we can identify two types of leakage: (1) leakage through the middle
of a logic gate across a voltage drop of $V_{\rm dd}$ when the gate's
supply rails are split, and (2) leakage through a turned-off pass
transistor across a voltage drop of $V_{\rm dd}/2$.  All these
leakages occur through off devices that have a $V_{\rm GS}$ of zero;
other off devices with $V_{\rm GS}<0$ have exponentially less leakage,
and so we ignore them.  During some transitions, there are also
leakages across voltage drops smaller than $V_{\rm dd}/2$.  Some of
these happen when $V_{\rm GS}<0$, and the others contribute small
amounts to the total leakage power.

One may carry out a careful analysis of leakage based on the timing diagram
of Younis's 3-phase clocking cycle.  We will not relate the analysis in
detail here.  However, one finds that for each signal wire, there is
leakage inside one of the logic gates that drive that wire during
$\frac{22}{24}$ of each cycle, and leakage through a pass transistor for
about $\frac{19}{24}$ of the cycle (this latter figure is adjusted to take
into account the smaller voltage drops that occur during transitions).

Further, the $I_0$ for the leakage inside logic gates may be different
than the $I_0$ for the leakage through the pass transistors, depending
on how the devices are sized relative to each other, and also
remembering that if a logic gate is not a simple inverter but rather
contains several parallel paths, there may be leakage through all of
the paths.

However, all of these factors can incorporated into our definition of
the effective $I_0$ for the SCRL signal wire, as follows.  Let $I_{\rm
0G}$ be the effective $I_0$ in the pullup/pulldown networks of our
logic gates (taking into account the widths of devices and number of
parallel paths).  Let $I_{\rm 0P}$ be the $I_0$ through our pass
transistors (taking into account their widths).  Then we just define
the effective $I_0$ for the single-transistor equivalent model of the
SCRL signal wire's average leakage as
\begin{equation}
I_0 = I_{\rm 0G}{\frac{22}{24}} + I_{\rm 0P}{\frac{1}{2}}\cdot{\frac{19}{24}}
\label{eq:i0}
\end{equation}
where the $\frac{1}{2}$ compensates for the fact that the leakage through
the pass transistors involves a voltage drop of $V_{\rm dd}/2$ rather than
$V_{\rm dd}$.  This substitution is valid because the other factor in
eq.~\ref{eq:ileak} (the exponential) doesn't depend on the magnitude of the
$V_{\rm DS}$ voltage drop or on which kind of leakage we are looking at,
since $V_{\rm GS}=0$ for all the significant leakage.

We further note that almost all of the leakage takes place when
$V_{\rm GS} = 0$ and $V_{\rm SB}=0$, so that at these times $V_{\rm
T}=V_{\rm T0}$, and we can substitute $V_{\rm T0}$ for $V_{\rm T}$ in
eq.~\ref{eq:ileak}.  Further, for conciseness let's define convenient
notations for the thermal voltage $k_{\rm B}T/q$ with and without the
$(1+\alpha)$ fudge factor.
\begin{eqnarray}
\Vth &\equiv& k_{\rm B}T/q \\
\Vth' &\equiv& (1+\alpha)\Vth
\end{eqnarray}
Now we can re-express the leakage current as just
\begin{equation}
I_{\rm leak} \approx I_0 e^{-V_{\rm T0}/\Vth'}.\label{eq:ileak2}
\end{equation}

Although the above method for estimating $I_{\rm leak}$ was developed
for the particular case of static 3-phase SCRL, it is fairly clear
that the same approach could be carried out similarly for other SCRL
clocking schemes as well, with appropriate modifications to
eq.~\ref{eq:i0}.  Remember, however, that in 2-phase SCRL, nodes are
not always being actively driven, and so high leakages can harm
functionality as well as dissipating power; therefore the analysis
later in this section will probably not be appropriate for dynamic
2-phase clocking.

Now that we've gotten $I_{\rm leak}$ expressed in terms of $V_{\rm
T0}$, let's merge eqs.~\ref{eq:pleak} \& \ref{eq:ileak2} back into our
expression for $E_{\rm min}$ (eq.~\ref{eq:emin}):
\begin{eqnarray}
E_{\rm min} &=& \left(2\sqrt{2 c_{\rm dd} n_{\rm t}}\right) C_{\rm L}
     \sqrt{\frac{V_{\rm T0} P_{\rm leak}}{ k}}\\
&=& \left(2\sqrt{2 c_{\rm dd} n_{\rm t}}\right) C_{\rm L} \cdot \nonumber \\
& &\sqrt{\frac{V_{\rm T0} (n_{\rm dd} V_{\rm T0}) I_0 e^{-V_{\rm T0}/\Vth'} 
	}{ k}} \\
 &=& \left(2\sqrt{2 c_{\rm dd} n_{\rm t} n_{\rm dd}}\right) \cdot \nonumber \\
  && C_{\rm L} V_{\rm T0} \left(\sqrt{\frac{I_0}{ k}}\right)
	e^{-{\frac{1}{2}}V_{\rm T0}/\Vth'}
\end{eqnarray}

To make this formula easier to work with, we'll express the factor
involving the SCRL power and timing parameters $n_{\rm dd}$ and $n_{\rm t}$
as just $s$.  Also, we note that since $I_0$ and $k$ both scale roughly
proportionally to transistor width, the voltage factor $\sqrt{I_0/k}$ is
basically independent of transistor width.  It scales up with increasing
length however (because $k$ scales down proportionally, but $I_0$ does not
scale down as much), indicating that SCRL favors designing with
minimum-length devices and small gate fan-ins.  (Larger fan-ins yield a
larger effective length.)  In such designs, $\sqrt{I_0/k}$ can be thought
of as a width-independent voltage $v_{\rm c}$ that is characteristic of the
particular device technology being used.  It can be interpreted as the
drive voltage required to turn on a standard-length transistor strongly
enough to conduct current at some fixed multiple of the transistor's
zero-drive leakage current $I_0$.\footnote{Perhaps $v_{\rm c}$ is related
to the drive voltage needed for strong inversion.  This needs further
investigation.}

Given the above definitions, we can re-express the minimum energy as
\begin{eqnarray}
s   &\equiv& 2\sqrt{2 c_{\rm dd} n_{\rm t} n_{\rm dd}} \\
    &   =  & 2\sqrt{\frac{2 n_{\rm t} n_{\rm dd}^3}{ 3n_{\rm dd}-4b_{\rm avg}}} \\
v_{\rm c} &\equiv& \sqrt{I_0/k} \\
E_{\rm min} &=& s C_{\rm L} v_{\rm c} V_{\rm T0} 
		e^{-{\frac{1}{2}}V_{\rm T0}/\Vth'}.\label{eq:EvsVT0}
\label{eq:emin2}
\end{eqnarray}

\begin{figure}
\centerline{\psfig{file=evsvt0.epsi,width=3in}}
\caption[How minimum energy scales with threshold voltage]
{How minimum energy/operation scales with $V_{\rm T0}$ in SCRL, as
per~\eqref{eq:EvsVT0}.  The curve is only meaningful for points to the
right of the maximum, but not too far to the right.  At the very low
voltages at the far left, circuits will not function properly because they
will be overwhelmed by leakage currents.  At very high voltages far to the
right, gate oxides may break down, depending on their thickness.  But up to
this breakdown point, SCRL minimum energy scales down roughly
exponentially, as the ratio $V\tg{T0}/\Vth$ is increased.}
\label{fig:evsvt0}
\vspace{0.1in}
\hrule
\end{figure}
Figure \ref{fig:evsvt0} shows qualitatively how $E_{\rm min}$ scales
as $V_{\rm T0}$ is changed.  Perhaps surprisingly, above a certain
point, the minimum energy/op of SCRL actually decreases exponentially
as the threshold voltage is increased!  This contrasts with the
situation in standard CMOS, where higher thresholds mean quadratically
larger switching energy, determined by equations like
eq.~\ref{eq:cv2}.  The difference in SCRL is that higher thresholds
mean exponentially smaller leakage power, which allows us to run at
exponentially slower speeds and still not have leakage dominate the
total energy, which thus allows exponentially less energy to be
dissipated during our quasistatic charging at high thresholds.

The curve in fig.~\ref{fig:evsvt0} also suggests that at very low
thresholds, the energy/op can be made arbitrarily small as well.  However,
this part of the curve is probably not accurate.  Further analysis
({\cite{memom3}}) shows that the maximum point on the curve occurs when
$V_{\rm T0}=2\Vth'$, twice the adjusted thermal voltage.  At thresholds
near or below the thermal voltage, a $V_{\rm dd}$ that is only a small
fixed multiple of the threshold voltage will probably not be high enough to
produce strong inversion, and the square-law equation (\ref{eq:sqlaw}) will
probably not accurately represent the source-drain current of our
transistors, upon which the above analysis was based.  Moreover, at low
thresholds, the high leakage power will call for a very short rise time
from eq.~\ref{eq:tr}; if the rise time is too short, it will not be large
compared to the effective $RC$ of our transistors, which will invalidate
the assumptions upon which the analysis of section \ref{sec:scrldiss} was
based.

Also, all of the analysis above is only reasonably accurate for relatively
large devices.  As we mentioned {\ref{sec:perarea}}, as transistors shrink
below present-day sizes, a variety of short-channel effects become
increasingly significant in their influence on the I-V characteristics of
the device.  As we move deeper into this short-channel regime, the
analytical expressions on which the above sections were based will become
increasingly inaccurate.  It was deemed beyond the scope of the present
work to correct all of the above analysis to take short-channel effects
into account, although such corrections will be important if adiabatic
techniques are to be applied to low-energy computing applications in the
near future.

\subsection{Fixing a problematic case for plain SCRL}
\label{sec:scrlsnag}

We believe there may actually be a small problem in ordinary SCRL, as
originally described by Younis and Knight, a problem that seems to lead to
non-time-proportional dissipation, and perhaps even to a dissipation per
operation that is bounded below by $\kT$ (although this is not yet
certain).  This particular problem occurs even at low temperatures, at
which ordinary leakage currents become exponentially more insignificant.

The problem occurs in multi-input SCRL gates such as NAND and NOR gates, as
well as in more complex gates, but not in single inverters.  The problem is
due to the fact that under some inputs, part of a pull-up or pull-down
network may be conducting even if the whole network is not.  So for
example, in a NAND gate, when the output is high, part of the pull-down
network may actually be pulled up as well (see fig.~\ref{fig:scrlsnag}).
So an {\nFET}, which is designed for passing low voltage, is being asked to
pass a high voltage.  {\nFET}s can only conduct well over part of the high
range, up to a threshold drop $V\tg{T}$ away from the high voltage
$V\tg{dd}$.  So, an internal node in the pulldown network will follow the
output ramp closely up to this voltage, but after that its rate of increase
will slow down, because the effective resistance of the {\nFET} increases
exponentially as its source voltage rises several thermal voltages $\Vth$
above the threshold point.  Therefore, the voltage drop over this {\nFET}
will become significantly larger than voltage drops in the rest of the
circuit, and some non-zero amount of charge will flow over this voltage
drop, as the {\nFET} source voltage gradually edges up to a few thermal
voltages above $\Vdd-V\tg{T}$.

\begin{figure}
\centerline{\psfig{file=scrl-snag.epsi,width=5in}}
\caption[A problematic case for SCRL]{A case in the simplest version
of SCRL where there may be energy dissipation that does not scale down in
proportion to operating frequency.  Consider a NAND gate when the inputs
are different, and the higher input goes to the innermost {\nFET}.  When
the rails split, that {\nFET} will conduct, and the internal node voltage
$V\tg{x}$ will track $V\tg{out}$ arbitrarily closely (depending on the ramp
time), until $V\tg{x} \approx \Vdd-V\tg{T}$.  Then, the FET will begin to
cut off, and $V\tg{x}$ will lag farther behind $V\tg{x}$, while it
continues to increase over a range of several additional $\Vth$'s.  In the
depletion regime, it takes several $\Vth$'s worth of $V\tg{GS}$ voltage
change in order for a MOSFET's channel charge (and thus its conductance) to
fall off by several factors of $e$.  During this time, drain voltage
continues to increase at a relatively faster rate and so charge will be
falling over a relatively large voltage drop.  NOR gates and more complex
gates will suffer from this problem as well.}
\label{fig:scrlsnag}
\vspace{0.1in}
\hrule
\end{figure}

Clearly, this situation will have some impact on the analysis of the energy
dissipation of SCRL, but it is not yet clear exactly what the impact will
be.  It is difficult to derive an analytical expression for the dissipation
due to this effect.  However, it seems likely that the major result will be
that the overall dissipation of SCRL circuits does not decrease anywhere
near as quickly as linearly with frequency, once the overall dissipation is
low enough that the dissipation due to the above effect becomes
significant.

To test this intuition, I performed a simple numerical simulation of this
situation for an example circuit, and found that when the ramp time was
long enough so that the total dissipation in the earlier part of the ramp
was less than $\kT$, the dissipation in the subthreshold regime was still
$\sim 3000\,\kT$---but it was still decreasing slowly as the ramp time was
lengthened.  If the ramp time was lengthened far enough, perhaps the source
voltage would continue to track the ramp closely all the way up to $\Vdd$,
and the dissipation in this transistor would be less than $\kT$---but then
we are talking about ramp times so long that energy losses due to leakage
would be significant, and greater than $\kT$, in other parts of the
circuit.  The logic would no longer function reliably because leakage
currents would be comparable to charging currents.  Overall, it is not yet
clear whether or not this effect leads to a true $\sim\kT$ lower bound on
dissipation in these simple circuits.

Fortunately, regardless of the precise effect, there is a simple way to fix
SCRL to prevent this problem from occurring, and restore guaranteed
time-proportionate reversibility to SCRL.  That fix is to transform the
problematic transistors into CMOS pass gates, with appropriate inputs,
which conduct well over the entire voltage range that they might encounter.
Thus, at low speeds the voltage drop across the transistors will always
remain insignificant.  The NAND gate problem in figure~\ref{fig:scrlsnag}
can be repaired via the addition of just a single {\pFET}, as shown in
fig.~\ref{fig:scrlfix}.

A more general way to fix all SCRL logic gates would be to just use
dual-rail (complementary) logic everywhere, to ensure that the appropriate
complementary signal for use in pass gates is available.  This would have
the advantage that it would also eliminate the need for 2-level retractile
cascades in non-inverting logic stages, and would lead to greater
data-independence of the overall capacitance of the chip, allowing the
resonant power supply signal to be tuned more cleanly.  The primary
disadvantage would be the need for a roughly factor of 2 increase in the
number of gates, wafer surface area, and entropy coefficient.  But in the
spirit of the asymptotic emphasis of this thesis, we remind ourselves that
this is only a small constant factor.

\begin{figure}
\centerline{(a)\psfig{file=scrl-fix.epsi,width=2in}
(b)
\begin{minipage}[b]{3in}
\small
\begin{tabular}{|c|c||c|c|c|c|}
\hline
         &           &                       &       &       & PDN       \\
A	 &  B        &  T1                   &  T2   &  T3   & Conducts? \\
\hline
\zerobit &  \zerobit &  off                  &  off  &  on   & no        \\
\zerobit &  \onebit  &  off                  &  on   &  off  & no        \\
\onebit  &  \zerobit &  on $\rightarrow$ off &  off  &  on   & no        \\
\onebit  &  \onebit  &  on		     &  on   &  off  & yes       \\
\hline
\end{tabular}
\end{minipage}}
\caption[Fixing the problem case]{A simple way to eliminate the problem
discussed in figure~\ref{fig:scrlsnag}.  A {\pFET} ``T3'' tied to input B
is placed in parallel with the inner {\nFET} ``T1''.  T3 will be fully
turned on in the problem case where $\text{A}=\onebit$ and
$\text{B}=\zerobit$, and thus node $V\tg{x}$ will follow $V\tg{out}$ all
the way up to $\Vdd$, and so there will be no problematic voltage drop over
T1.  The truth table on the right verifies that the logic of the pulldown
network remains correct in all cases with the addition of T3.}
\label{fig:scrlfix}
\vspace{0.1in}
\hrule
\end{figure}

That concludes our discussion of general properties of SCRL.  In the next
section we discuss the particular SCRL-based circuits that we designed and
fabricated.

\section{Experimental SCRL Circuits}
\label{sec:scrlexp}

The first SCRL circuits to be fabricated were those of Younis
{\cite{Younis-94}} in his original experimental tests.  Younis fabricated a
demonstration chip that included reversible adders and multipliers.  Younis
tested these chips and measured their power dissipation, and found that it
scaled roughly as predicted within the range of sensitivity of the
measurements.  More accurate measurements of dissipation in other
adiabatic circuits have been performed by Solomon and Frank (1995,
{\cite{Solomon-Frank-95}}).

In parallel with my own work, Carlin Vieri has been designing Pendulum, a
fully-adiabatic RISC-style processor based on SCRL.  I assisted Vieri with
various Pendulum instruction set issues, about which I will have more to
say in chapter~\ref{ch:program}.  Scott Rixner and I designed and tested
Tick, a non-adiabatic 8-bit version of Pendulum that was intended to gauge
the complexity of the reversible instruction set design.  (Unfortunately,
the chip failed to operate fully, due to inaccuracies in the layout
design-rule checking software that we used; design modifications would be
necessary to get Tick working.)  As of this writing, the fabrication of the
fully adiabatic Pendulum prototype has recently been completed, and it is
now in the testing phase.

Vieri and colleagues have also designed and fabricated XRAM
{\cite{Vieri-95}}, a fully-adiabatic static memory component, whose design
I discussed with Vieri, but was not intimately involved with.

The primary SCRL design effort that I have been centrally responsible for
(with assistance from other group members) has been the design of
{\FlatTop}, a chip comprised of an adiabatic mesh-style array of processing
elements that are very simple, yet capable of fully universal reversible
computation.  The {\FlatTop} chips can be tiled in 2-D or 3-D arrays, and
together with the appropriate external resonant rail generators, reversible
communications links, and power delivery/entropy removal systems, would
constitute a concrete example of a time-proportionately reversible 3-D mesh
processor, such as we conjectured was asymptotically optimal in
ch.~\ref{ch:scaling}.  As such, sufficiently large arrays of {\FlatTop}
chips would be, in principle, faster for their size than any possible
irreversible machine.  At least, this would be the case if the {\FlatTop}
design was repaired to circumvent the dissipative flaw in SCRL that we
discussed in~\S\ref{sec:scrlsnag}, which had not yet been discovered at the
time {\FlatTop} was designed.  Also, in reality the {\FlatTop} machine
sizes necessary to outperform the fastest irreversible architectures would
be astronomically large.  But {\FlatTop} is still an important
proof-of-concept, demonstrating that it is not only possible but fairly
straightforward to design a universal, sequential reversible mesh processor
using fully adiabatic circuits.

We now discuss some of the background for the {\FlatTop} design.

\subsection{The Billiard Ball Model}
\label{sec:bbm}

The basic operation of {\FlatTop} is to simulate the ``Billiard Ball
Model'' (BBM) of computation, an idealized physical model of reversible
computation that was introduced by Fredkin {\cite{FredToff82}} in the
course of some of his early work on reversible logic circuits.  The model
involves computation using idealized perfect spheres, that move
ballistically through 2-D space along precise trajectories, and bounce off
fixed walls and each other in perfectly elastic collisions.  Fredkin showed
that using only this behavior, one can construct elementary reversible
boolean logic gates (fig.~\ref{fig:bbgates}) and put them together to
compose arbitrary reversible logic circuits.

\begin{figure}
\centerline{\psfig{file=bbgates.epsi,width=4in}}
\caption[Two logic gates in the physical billiard ball model]
{Examples of two logic gates in the physical billiard ball model of
computation.  The ``Crossover Gate'' on the left permits two ball-signals
to effectively pass through each other without delay.  The ``Feynman Gate''
on the right computes a reversible AND/NAND function.}
\label{fig:bbgates}
\vspace{0.1in}
\hrule
\end{figure}

The BBM is of course an idealization.  In reality, to avoid the
accumulation of errors in ball trajectories, the balls would have to be
made to travel along troughs in a potential energy surface, pushed along by
waves of potential to keep their global timing consistent, and to make up
for frictional losses.  In reality, the collisions would not be perfectly
elastic---but this is just an example of time-proportionate reversibility,
since real collisions between hard objects become more nearly elastic as
the speeds involved are decreased.  Energy can be injected into the system,
at a rate per interaction that declines with the balls' speed, to keep the
system progressing forwards at a constant rate.  In talks given at MIT,
Fredkin has discussed physically plausible mechanisms for performing the
above-mentioned types of corrections.  {\ed{Norm, has Fredkin published
those ideas anywhere?}}

But the main conceptual importance of the model is that it provides a way
to see how extremely simple interactions---ball collisions---can be used to
build up arbitrarily complex logic circuits.  Further, in essence it is a
purely digital model.  It only cares about discrete positions and times.
In contrast, other researchers have investigated analog models of
computation in which an unlimited number of decimal places of precision in
physical parameters are used to carry information important to computation
{\cite{Vergis-etal-86,SmithWD-93,Siegelmann-93}}, but such models are not
physically realistic, because in quantum mechanics, bounded systems only
have a finite number of distinguishable states, as we noted
in~\S\ref{sec:Sdensity}; infinite precision is not a physically realistic
assumption.

Furthermore, the BBM is ultimately a parallel model of
computation---interactions may be occurring in many parts of the space
simultaneously---and a 3-D version of it could asymptotically efficiently
simulate any (non-quantum) physical algorithm.

Due to its ultimate digital nature, its simplicity, its reversibility, its
asymptotic efficiency, and its universality, the billiard ball model is a
useful starting point for investigations of reversible computation.

\subsection{The Billiard Ball Model Cellular Automaton}

Making the ultimately digital nature of the billiard ball model even more
apparent, in 1983 Norman Margolus invented a digital cellular automaton,
with only 1 bit per cell, that precisely and efficiently simulates the
billiard ball model on a 2-D grid of cells
{\cite{Margolus-84,Margolus-88}}.  In this ``Billiard Ball Model Cellular
Automaton'' (BBMCA), balls are represented by pairs of 1-bits that move
along diagonal paths through the grid of cells.  The grid is updated by
breaking it into two overlapping meshes of 2$\times$2 blocks of cells
(fig.~\ref{fig:margneigh}a), which apply on alternate update steps, and
within each block transforming its state according to a simple reversible
update rule (fig.~\ref{fig:margneigh}b).  The reader should be warned that
it is somewhat non-obvious how this update rule leads to behavior that
imitates the billiard ball model; see {\cite{Margolus-84}} or~{\S}2.4 of
{\cite{Margolus-88}} for a detailed description.

\begin{figure}
\centerline{(a)\psfig{width=1.5in,file=margneigh.epsi}
(b)\psfig{width=2.5in,file=bbmrules.epsi}}
\caption[The billiard-ball model cellular automaton]
{The Billiard-Ball Model Cellular Automaton.  (a) Updates are performed
alternately in two overlapping meshes of 2$\times$2 blocks of cells.  This
partitioning scheme, also called the ``Margolus neighborhood,'' is an easy
way to produce a global reversible dynamics from a local reversible update
rule.  (b) BBMCA block update rule.  In a 2$\times$2 block of cells, a
single 1-bit moves to the opposite corner of a block (propagation), whereas
2 bits in opposite corners move to the other 2 corners (collision).  All
rotations of the illustrated cases also apply.  All other configurations
remain unchanged.  Note that this rule is reversible.}
\label{fig:margneigh}
\index{BBMCA!rules for updating}
\vspace{0.1in}
\hrule
\end{figure}

Because of the extreme simplicity of the BBMCA update rule, we chose it as
our target for our proof-of-concept mesh architecture, which was therefore
named {\FlatTop}, after the local billiards pub, ``Flat-Top Johnny's.''
This architecture is not intended to be particularly efficient in terms of
its constant factors, or to be particular easy to program directly.  But
ultimately, since it can asymptotically efficiently simulate any
(non-quantum) parallel architecture, it demonstrates the points we are
trying to make about asymptotic scaling.  Given a large enough array of
{\FlatTop} chips, one could efficiently simulate any alternative
architecture or programming model on top of it.

A more practical reversible mesh processor would probably have a design and
a programming model closer to that of Vieri's RISC-style Pendulum chip.  In
fact, given a suitable communication network between neighboring
processors, Pendulum itself would probably work fine as a processing
element.  But {\FlatTop} was relatively easy to design, and it gives us the
proof-of-concept we wanted.  It also seems entirely possible to design a
reversible FPGA element that would be intermediate in complexity and
programmability between {\FlatTop} and Pendulum, and might permit greater
logical density on a wider variety of problems than either.

\subsection{Logic minimization}

After choosing the BBMCA as the target functionality, the next step was to
translate the BBMCA update rule into a boolean logic expression that could
be easily implemented in a real SCRL logic circuit.  After trying several
ways of translating the update rule into a boolean formula, we settled on
the solution shown in fig.~\ref{fig:bbmcalogic}, which is the simplest such
representation of the logic that we have found so far.

\begin{figure}
\centerline{\psfig{file=bbmcalogic.epsi,width=3in}}
\caption[Boolean logic form of BBMCA update rule]{Boolean logic form of
BBMCA update rule.  The S bit is true when there are bits in both
diagonals, in which case the block should remain {\emph{static}},
unchanged.  If there aren't bits in both diagonals, the block may change,
and a given bit (e.g., A) should turn on if it was off and the opposite bit
was on (propagation rule) or the two adjoining bits were on (collision
rule).}
\label{fig:bbmcalogic}
\vspace{0.1in}
\hrule
\end{figure}

The idea behind these formulas is that under the BBMCA update rule, one of
two things happen: either the block might change, or it must stay the same.
It must stay the same if there are 1 bits in both of the two diagonals
across the block.  Letting ``S'' represent this case, we have (with
reference to fig.~\ref{fig:bbmcalogic}) that S is (A or C) and (B or D).

Then, the new value of A itself, A$^\prime$, is fairly easy to compute.  If
S, then A$^\prime$ is just A, unchanged.  Otherwise, A$^\prime$ turns on if
and only if A was originally off, and either the opposite bit was on
(propagation rule), or both of the adjacent bits were on (collision).  If
all bits are off, they all remain off.  One can see by inspection of the
possible cases that this rule yields exactly the BBMCA update rules.

To implement this logic in SCRL, we would need at least two logic stages in
each processing element: The first stage would take the initial state of
the 4 cells in a block as input, and would produce the S signal using a
complex gate implementing the formula for S, while passing the input bits
through unchanged to the second stage.  The second stage would use a
complex gate for each cell to compute its new state given S and the
original cell states.  This was the basic function of each processing
element.  Since we were using 3-phase SCRL, a third stage was needed to put
the data in the correct phase for passing to an adjacent processing
element.  We also used the third stage to implement a special shift
register functionality for initializing the whole array.

\subsection{FlatTop array design}

Figure~\ref{fig:pegrid} outlines how the array of processing elements was
connected.  The horizontal-vertical grid shows the cell space partitioned
according to the Margolus neighborhood into 2 overlapping grids of
2$\times$2 blocks, as in fig.~\ref{fig:margneigh}a.  The updating of each
block is handled by a corresponding processing element, which can be
visualized as resting at the center of that block.  The state of each cell
is passed back and forth along wires between the PE's at the centers of the
two diagonally-overlapping blocks that contain the given cell.  The array
of PE's thus naturally forms a mesh that is oriented at a 45$^\circ$ angle
relative to the original CA mesh.  We orient the chip edges along this
diagonal mesh, so that the wires between processing elements can be
parallel to the chip edges, which is a constraint required by some
fabrication processes.

\begin{figure}
\centerline{\psfig{file=pegrid.epsi,width=\textwidth}}
\caption[Grid of {\FlatTop} processing elements]
{Schematic illustration of a grid of {\FlatTop} processing elements.  Each
2$\times$2 block of cells in the Margolus partitioning (see
fig.~\ref{fig:margneigh}a) is updated by a different PE.  The state of a
given cell is stored, on alternate time steps, on one or the other of the
two wires running between diagonally adjacent PEs.  The PEs thus naturally
form a square mesh oriented 45$^\circ$ from the BBMCA mesh.  To make layout
more convenient, the chip edges were oriented parallel to the PE mesh.}
\label{fig:pegrid}
\vspace{0.1in}
\hrule
\end{figure}

One artifact of this design is that, if all the processing elements operate
simultaneously, they will actually be simulating two parallel
non-interacting BBMCA systems.  We can separate the PEs into ``dark'' and
``light'' processors in a diagonal checkerboard pattern as pictured.  One
CA system is the one that is processed by light processors on even-numbered
time-steps and by dark processors on odd-numbered steps.  The other CA
system is the one that is processed by dark processors on even-numbered
steps and by light processors on odd-numbered steps.  The two systems do
not interact at all, and they can be used to represent two completely
different configurations of balls and mirrors in the BBM.  Using both
systems can be seen as a way of making more efficient use of the hardware,
which would otherwise be only half utilized.

The two systems can be connected together at one or more chip edges to form
one larger system with an alternative topology.  In fact, we did this in
our prototype {\FlatTop} chip.  Also, at various points at the chip edges
we passed signals to bidirectional I/O pads to connect to neighboring
processors in a larger array.  Normally in the BBMCA the grid is 2-D, but
there is nothing to prevent a topology that is locally 2-D on-chip, but
globally 3-D, with the chips connected in a 3-D mesh.  As long as each chip
has at least 3 external connections, a globally 3-D network can be made
{\cite{Ward-etal-91}}.

Appendix~\ref{ch:ft} shows most of the Cadence schematics and layout for
the {\FlatTop} unit cell and processor array.  The design was simulated
using Verilog and functioned as expected in simulation.  Individual PEs
were simulated in HSPICE to verify that there were no errors causing $CV^2$
dissipation.  The chips have been fabricated but have not yet been tested.
It is expected that their basic functionality will work, and that fairly
low-energy operation is possible, but that the dissipation will not be
quite as low as was originally projected due to the SCRL flaw we discussed
in~\S\ref{sec:scrlsnag}.

\subsection{Minimum energy estimation}

After designing {\FlatTop}, we carried out an approximate hand-analysis of
the circuit, using the device parameters of the fabrication process we used
(table~\ref{tbl:cap}), and the formulas we derived in~\S\ref{sec:adjspeed}
(p.~\pageref{sec:adjspeed}), to estimate the circuit's minimum energy
dissipation per operation when operated at 3.3 V, the standard supply
voltage for the process (HP14) that was used.  As the circuit is clocked
more slowly, switching energies decrease proportionally, but leakage
energies increase.  As we pointed out in~\S\ref{sec:adjspeed}, the minimum
total energy per operation turns out to be achieved at the speed at which
switching energy equals the leakage energy (refer back to
fig.~\ref{fig:evstr}, p.~\pageref{fig:evstr}).

\begin{table}
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\multicolumn{2}{|c|}{NMOS} & \multicolumn{2}{c|}{PMOS} \\
\hline
Var & Value & Var & Value \\
\hline
$\phi_{0}$ & 1.1V & $\phi_{0}$ & 0.8993 \\
\hline
$m_{\rm j}$ & 0.726 & $m_{\rm j}$ & 0.4905 \\
\hline
$m_{\rm jsw}$ & 0.2451 & $m_{\rm jsw}$ & 0.2451 \\
\hline
$C_{\rm j}$ & 4.67x10$^{-4}$ F/m$^2$ & $C_{\rm j}$ & 8.76x10$^{-4}$ F/m$^2$ \\
\hline
$C_{\rm jsw}$ & 3.20x10$^{-10}$ F/m & $C_{\rm jsw}$ & 2.13x10$^{-10}$ F/m \\
\hline
$t_{\rm ox}$ & 9nm & $t_{\rm ox}$ & 9nm \\
\hline
$\mu_{\rm n}$ & 978.1 cm$^2$/V$^2$-s & $\mu_{\rm p}$ & 228.5 cm$^2$/V$^2$-s \\
\hline
$C_{\rm ox}$ & 3.89x10$^{-15}$ F/$\mu$m$^2$ & $C_{\rm ox}$ & 3.89x10$^{-15}$ F/$\mu$m$^2$ \\
\hline
${k'}_{\rm n}$ & 3.80x10$^{-4}$ A/V$^2$ & ${k'}_{\rm p}$ & 8.889x10$^{-5}$ A/V$^2$ \\
\hline
\end{tabular}
\end{center}
\caption[Device parameters for the HP14 fabrication process]
{Device parameters for the HP14\index{HP14} process, from
Cadence\index{Cadence} models.  These figures were used in our
hand-calculations of the minimum energy dissipation per operation in
{\FlatTop}.  {\ed{What about $I_0$?}}}
\label{tbl:cap}
\vspace{0.1in}
\hrule
\end{table}

The energy estimation procedures we used are also described in more detail
in our conference paper {\cite{Frank-etal-98a}} on {\FlatTop}.  The upshot
was that the optimal cycle time turned out to be around 12$\micro s$, at
which point {\FlatTop} would dissipate around 10 fJ per cycle per cell,
whereas in our estimation the equivalent iCMOS circuit dissipates around 20
pJ, a reduction of energy dissipation by a factor of 2000!  When cooled
below room temperature, the chip would have less leakage, and even greater
energy efficiency could be obtained at lower speeds.

Unfortunately, there has not yet been an opportunity to actually test the
energy dissipation in {\FlatTop}.  Indeed, such low levels of dissipation
would be hard to measure accurately.  Also, the actual dissipation is
probably higher than we first estimated, since at design time we did not
know about the SCRL bug mentioned in~\S\ref{sec:scrlsnag}.  However, if
this bug were fixed, we believe that dissipation in the chip would be
roughly as predicted.

\section{Resonant power supply techniques}

In most of the above, we have glossed over the issue of how to build a
resonant power supply that can provide the power/clock waveforms that SCRL
requires, in such a way that the energy loss per cycle scales down
arbitrarily in proportion to frequency.  This particular issue has not been
the primary focus of my own research, but it is important for the overall
scaling results.

Various techniques for powering adiabatic circuits have been described in
the literature:
{\cite{Svensson-etal-94,Svensson-95,Younis-Knight-95,Frank-Solomon-96,Athas-etal-96}}.
However, many techniques do not have asymptotically zero dissipation.  One
interesting recent technique is the one developed in our group by Becker
and Knight {\cite{Becker-Knight-98,Becker-Knight-99}}.  This technique uses
a transmission line with tuned nonuniformities that allow it to end up
resonating with any desired waveform; in particular, it has been used to
produce the trapezoidal ramp-shaped waveforms used by SCRL{\footnote{As
reported by Becker in personal discussions.}}.  However, due to nonlinear
effects of the signal on resistivity in Becker's transmission lines, the
dissipation per cycle does not scale down quite in proportion to the
frequency $f$, but apparently rather as $\sqrt{f}$.  Thus the scaling
results for a reversible system powered by these circuits is not quite as
good as the ideal.

An open problem for adiabatic computing is the design of an external
resonant element that can provide waveforms usable for adiabatic computing
while at the same time retaining the property of having a dissipation per
cycle that scales down to arbitrarily small levels, in direct proportion to
frequency.  It is also important for the cost-efficiency arguments of
{\S\ref{sec:scaling-analysis}} that the cost of the resonant element does
not increase substantially as its frequency is decreased.  One problem with
using Becker's transmission line approach in reversible computing is that
the length of the transmission line scales up in proportion to its
frequency, therefore increasing the cost of the system when run at low
speeds.

However, we (optimistically) suspect that if enough attention is paid to
the issue of designing resonant power supplies, a power supply technique
having the desired properties can be found.  Certainly it has not been
proven, to our knowledge, that no such technique can exist.  It is an
important area for future work to determine with certainty whether an ideal
supply technique can exist, and to design a technique having the most
favorable scaling properties that are physically possible.

\section{Scaling SCRL to future technology\\
generations}
\label{sec:scrlscale}

Although it is difficult to precisely forecast the future performance of
CMOS-based technology in the near term (next 10 years), over the long term
one can point out some qualitative aspects of how performance scales with
technology shrinkage in CMOS-like circuits, based on some fundamental
scaling laws, and see how these factors affect SCRL compared with standard
irreversible CMOS.

Consider the effect of shrinking all circuit dimensions by a factor of
$\fl$ (that is, any length $\ell$ is shrunk to $\ell/\fl$).  Intuitively
speaking, one must consider the effect of shrinking all dimensions, rather
than just one or two, because any dimension that does not shrink will
eventually dominate in terms of its parasitic effects, and one could
improve performance by shrinking that dimension as well.

Under $\fl$ scaling in all dimensions, the width and length of capacitive
elements will decrease, but so will their thickness, so capacitances will
decrease by $\sim\fl$.  Resistive elements will get shorter, but also
narrower along the other two dimensions, so their resistance will increase
by $\sim\fl$.  Characteristic $RC$ delays through resistive elements thus
do not scale down by much, since these factors cancel out.  (In the near
term, resistance is dominated by the effective resistance through
transistors.  These are harder to model accurately.  But if their
resistance decreases, $RC$'s might decrease for a while, but then
eventually the resistance in the wires will come to dominate, so at some
point $RC$ cannot decrease further.)

Earlier, we saw that energy dissipation per operation in adiabatic
technologies such as SCRL scales as $CV^2\frac{RC}{t}$.  If the $RC$ part
doesn't improve much beyond a certain point, as we just saw, then what
about the $CV^2$ part?  This part corresponds to node energy.  For a while,
$C$ will scale down as $1/\fl$, and $V$ at some point will be forced to
scale down at least as fast as $1/\fl$ because otherwise, as gate oxides
get thinner, the electric field through the oxide would increase and at
some point would break down.  So $CV^2$ eventually must scale down at least
as fast as $\fl^{-3}$.  This makes sense intuitively, because it
corresponds to the energy density in the circuit not increasing beyond a
fixed maximum level that the circuit's materials can withstand.

But, can $CV^2$ continue to decrease indefinitely?
In~\S\ref{sec:cmosentgen}, p.~\pageref{sec:cmosentgen}, we already
demonstrated that in irreversible CMOS, we can show that $CV^2$ cannot
decrease below a reliability-dependent factor times $\kT$ from a pure
thermodynamics argument.  But this reliability-based limit affects SCRL as
well.  The electrons in a circuit at normal temperatures behave like a
thermal gas, and this leads to a well-known noise component called ``$kT/C$
noise,'' because anything that samples a signal will find that the
$\sigma^2$ variance in the sampled voltage is $\kT/C$, where $C$ is the
capacitance of the sampling node (\cf\ p.~\pageref{pg:kToverC}).  Such
sampling occurs in SCRL all the time; each time a pass gate in an
bidirectional latch cuts off, it can can be viewed as sampling the previous
logic gate's output voltage on a sampling node whose capacitance is just
the load capacitance of the latch output.  If thermal noise causes a
sampling error comparable to $V\tg{dd}/2$, correct logical functionality
can be impaired.  Therefore, just like in irreversible CMOS, node energies
in SCRL cannot be made smaller than a reliability-dependent factor times
$\kT$.

Therefore, as typical node energies decrease with $\fl^{-3}$ at a given
temperature, eventually they will reach this point where further decreases
cannot be made without sacrificing reliability, so to continue shrinkage,
the temperature will have to start scaling down as $\fl^{-3}$ as well.  But
note that at this point, the entropy generation per operation in SCRL is no
longer decreasing along with the shrinkage.  We know $S=E/T$, and the
dissipation $E$ is decreasing as $f^3$, but now so is $T$.  So ultimately,
SCRL's entropy generation per operation becomes exactly $RC/t\tg{r}$ times
a reliability-dependent constant ($\ln N$), regardless of further circuit
shrinks.

Further decreases in entropy coefficients beyond this point would require
non-scaling-related decreases in $R$, such as less resistive wiring
materials, a switching device with better I-V characteristics than MOSFETs
(perhaps mi\-cro-elec\-tro-mech\-an\-i\-cal switches, if they could be made
small enough), or even superconducting circuit elements.  Irreversible
CMOS, on the other hand, could not take full advantage of such
improvements, because its dissipation per operation does not fundamentally
improve with $R$, and its entropy generation per operation is bounded below
by $\sim\ln N\units{\nat}$.

This leads to a long-term advantage of SCRL as the technology scales.  As
lengths are shrunk by $\fl$, one can create $\fl^3$ times as many
processing elements out of a given mass of materials.  Beyond a point,
entropy generation for a fixed mass of reliable irreversible CMOS scales as
$\sim\units{\nat}$, whereas entropy generation in SCRL is
$\sim\frac{RC}{t\tg{r}}\units{\nat}$, where we assume we have reached a
limit where $RC$ cannot be decreased further.  But as the number of
processors increases with $\fl^3$, the clock frequency of the irreversible
machine must be slowed down for some tasks by a factor $\fl^{1/3}$, due to
the increasing number of processing elements and the heat-removal arguments
of~\S\ref{sec:sim3d}, whereas the SCRL machine only needs to be slowed by
$\fl^{1/4}$.  Therefore, as $\fl$ increases, the overall processing rate
$\procrate$ of the irreversible machine goes as $\fl^{2\:2/3}$
whereas the reversible machine goes as $\fl^{2\:3/4}$, for a
reversible advantage increasing as $\fl^{1/12}$ as devices shrink by a
factor of $\fl$.

The above analysis imagines that it is possible to continue scaling MOSFETs
without fundamental differences up to and beyond the point where
reliability constraints become dominant.  In reality, MOSFETs may hit a
wall for other reasons before this (\cf~{\cite{Mead-94}}), at which point,
we might have to switch to a radically different technology for further
improvements.  Different technologies might have different scaling
considerations, but in any irreversible technology, the lower bound of
$S=1\units{nat}$ still holds, and in any reversible technology, we expect
there will be a characteristic transition time parameter $t\tg{c}$, playing
a role similar to the $RC$ parameter in CMOS, that approximately gives the
entropy coefficient for the technology (the entropy goes below 1 to the
extent that $t$ goes above the characteristic transition time).  To the
extent that this expectation is true, the reversible advantage with
shrinking components will be at least the $\fl^{1/12}$ factor mentioned
above, and if the characteristic time were to scale down with the length
scale as well, so much the better for reversible technology.  In that case,
processing rate would scale as $\fl^3$, an advantage of $\fl^{1/3}$ over
irreversible technology.

\section{Mostly reversible computation}
\label{sec:partlyrev}

This thesis primarily focuses on the concept of {\emph{arbitrarily}}
reversible computation.  But there are of course benefits to be gained from
a more limited use of reversibility in digital circuits.  For example, one
could construct a processor's functional units using fully adiabatic
circuits, and use irreversible switching only to update the high-level
processor state between instructions.  Or, one could identify the
highest-power components of a chip (often, the long buses) and apply
energy-recovery techniques only to those sections (this is the direction
being explored by the ISI ACMOS group
{\cite{Athas-etal-97,Athas-etal-97b,Tzartzanis-Athas-99}}).

Such limited uses of reversibility are potentially quite beneficial in
highly energy-limited environments such as portable or embedded systems
{\cite{Frank-96,Athas-99}}.  And since reversibility need not be complete
in order to gain substantial energy savings in these applications, the
algorithmic overheads for full reversibility that we explored in
{\S\ref{sec:separation}} need not apply.

This line of work can lead to immediate practical, commercially viable
products, thereby introducing adiabatic circuit concepts to industry.
After this introduction, we expect that gradually over time, users will
come to demand more and more computational power using less and less
energy, and so the degree to which systems will need to rely on reversible
techniques will increase.  Eventually, we expect designs for energy-limited
systems will converge to encompass the arbitrarily-reversible sort of
architectures that we discuss in this thesis.

\section{Adiabatic Circuits---Conclusion}

In this chapter we reviewed the most immediately feasible technology for
reversible computing, namely the technology of adiabatic circuits.  We
discussed the prototype mesh-style processor that we constructed using this
technology, which is a proof of concept that illustrates that adiabatic
circuit techniques such as SCRL are powerful enough to implement fully
reversible parallel machines such as we proposed in ch.~\ref{ch:scaling}.  

The most important areas for future work on adiabatic circuits, in the
context of exploring the limits of computing, include:

\begin{itemize}
\item More thorough analysis of the precise performance characteristics of
SCRL (or similar techniques) compared with irreversible CMOS in near-future
technology generations, to obtain a more precise estimation of the cost
level above which reversibility confers a real advantage.
\item Research on directions in VLSI technology (such as MEMS switches or
superconducting materials) that might lead to much lower-resistance
switches, which would benefit adiabatic techniques much more than
irreversible techniques.
\item More research on resonant power supplies for adiabatic circuits, in
search of a technique whose dissipation scales down in proportion to
frequency, asymptotically all the way to zero, while still providing
waveforms that are suitable for use in SCRL or comparable adiabatic circuit
techniques.
\item Similarly, design of reversible or even ballistic interconnection
technologies for communication between adiabatic circuit chips.
\item Design of good parallel reversible processor architectures, building
on {\FlatTop} and Vieri's Pendulum work.
\end{itemize}

In summary, the future for reversible computing with adiabatic circuits
looks interesting, but several new developments are still needed before
adiabatic techniques could become competitive with traditional techniques at
affording cost-efficient supercomputing.  It may well be that in the short
run, more effective cooling systems (which benefit irreversible techniques
more than reversible techniques) will be easier to develop.  However, in
the long run there are limits to how much cooling systems can be
improved---and cooling a system does not ultimately reduce total energy.
Meanwhile, various factors on the horizon threaten the ability of CMOS
circuits to keep shrinking indefinitely.

Eventually, to gain further improvements in machine speed, it seems we may
well be forced to jump to an alternative, non-CMOS-like, computing
technology.  Interestingly, many of the alternative technologies that have
been proposed by various researchers are capable of efficient reversible
computation.  In the next chapter, we briefly survey some of these, and
then in chapter~\ref{ch:program} we go on to discuss issues in the
architecture and programming of reversible machines, regardless of the
details of the underlying reversible logic technology.

\index{circuits!adiabatic|)}

% End chapter.
\cleardoublepage
