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% devices.tex - Alternative reversible device technologies
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\chapter{Future reversible device technologies}
\label{ch:devices}

\def\draftid{$\ $Id: devices.tex,v 1.1.2.3.2.1 1999/05/11 19:54:51 mpf Exp $\ $}

In the previous chapter, we reviewed adiabatic circuits, the reversible
computing technology that is most similar to the irreversible semiconductor
technology that is the basis of essentially all present-day computing.

In this chapter, we look a bit farther afield, and review a number of
proposals that have been made for computing technologies that might
supersede traditional CMOS, once the limits of MOSFET technology are
reached, and manufacturing processes develop to the point where
constructing machines based on these alternative device technologies is
feasible and economical.  A number of the technologies we describe are
(time-proportionately) reversible, or at least have reversible variants.
We will describe the important parameters of these technologies that impact
the scaling issues we discussed in chapter~\ref{ch:scaling}.  We also will
review several proposals that have been made for advanced cooling
technologies.

We then calculate, using the formulas developed
in~\S{\ref{sec:rate-vs-area}}, p.~\pageref{sec:rate-vs-area}, how large a
reversible machine would have to be, in the various proposed reversible
technologies and under the various proposed cooling systems, in order for
it to be faster per unit area than a machine built using various
irreversible technologies.  Most of these calculations were previously
reported in~{\S}7 of our journal article {\cite{Frank-Knight-98}}.

\section{Cooling technologies}

Ordinary CPU chips in most present-day computers rarely dissipate more than
100~W of heat from a square centimeter of chip surface using normal passive
cooling mechanisms, such as conduction through a ceramic package, and
natural or forced convection through air.  The chip surface is normally at
least at room temperature (300~K), so the entropy flux attained by these
mechanisms is no larger than $F = 100 \units{\Watt} / (\kB (300 {\units{\Kelvin}}) \ln(2) / \unit{bit}) = {\e{3.5}{22}} {\units{\bit / \second\rmh\cm^2}}$.

David Tuckerman {\cite{Tuckerman-Pease,Tuckerman-PhD}} has created and
tested advanced semiconductor cooling systems which use forced convection
of liquid coolant through micron-scale channels etched into the back of a
silicon wafer.  He has experimentally verified cooling rates on the order
of $\sim 1000\units{W}$ from a square centimeter-size chip, and has
projected that higher rates are possible.

Drexler (1992, {\cite{Drexler-92}}), {\S}11.5.3, p.~332, has designed a
nanotechnological cooling system using a fractal plumbing network that
ought to be able to remove at least $10\unit{kW}/\cm^2$ of heat at 273~K
from a flat slab of material up to 1~cm thick.  This corresponds to an
entropy removal rate of $\e{3.8}{24}\units{bit/s\,cm^2}$.

This figure corresponds roughly to the heat flux in the cooling systems of
current-day nuclear reactors, which transport megawatts of heat through
massive pipes on the order of a square meter in cross-section.  (According
to an acquaintance in the nuclear engineering department.)

If entropy were to be encoded in some material at the atomic scale at a
density $\sdens$ of no more than 1 bit per cubic {\AA}ngstrom (roughly the
volume of a small atom), and the material moves nearly ballistically
through the computer at a speed of $v=1\units{m/s}$, the maximum entropy
flux $\sflux=\sdens v$ is $10^{26}\units{bit/s\,cm^2}$.  (Allowing most of
the machine's volume to be occupied by the cooling material.)

If the material instead moves at a tenth of the speed of light (a very fast
speed that is still easy to analyze since relativistic effects are small),
then the maximum flux is $\e{3}{33}\units{bit/s\,cm^2}$.

\begin{table}
\begin{center}
\begin{tabular}{ll}\hline\hline
                            &  Max entropy flux $\sflux$      \\
Cooling technology          &  in $\units{bits/s\,cm^2}$ \\
\hline
Digital optic fiber         &  $10^{13}$                 \\
Typical passive emission    &  $\e{3.5}{22}$             \\
Drexler's fractal plumbing  &  $\e{3.8}{24}$             \\
Slow atomic ballistic       &  $10^{26}$                 \\
Fast atomic ballistic       &  $\e{3}{33}$               \\
Quantum maximum             &  $\e{5}{40}$               \\
\hline\hline
\end{tabular}
\end{center}
\caption[Maximum entropy flux estimates]{Estimates of the maximum
entropy flux per unit area achievable with various existing and hypthetical
cooling technologies.  These are all rather rough estimates, and the last
limit is especially arbitrary, since it is technically only valid for black
holes having an arbitrarily-chosen $1\units{\Ang}$ radius.}
\label{tab:cooling}
\vspace{0.1in}
\hrule
\end{table}

For materials around the density of water, $1\units{g/cm^3}$, Bekenstein's
fundamental quantum-mechanical/general-relativistic bound on entropy
(see~\S\ref{sec:blackhole}, p.~\pageref{sec:blackhole} and \cite{Bek84})
implies that even if all the material's mass-energy could be used for
storing information, no more than about $\e{1.7}{6}$ bits can exist in an
region 1 {\Ang} across.  At a tenth the speed of light this gives an
entropy flux of $\e{5}{40}\units{bit/s\,cm^2}$.

If entropy is removed digitally through 1 mm wide 100 GHz optical
fiber available today, the maximum flux is only about
$10^{13}\units{bits/s\,cm^2}$.  The maximum entropy flux that can be
achieved using electromagnetic radiation is the blackbody flux, as we
described with eq.~\ref{eq:FS-vs-FE} (\S\ref{sec:fluxlim},
p.~\pageref{eq:FS-vs-FE}).  We should note that the entropy density
$S/\volume$ in a thermal photon gas scales in proportion to $T^3$
(\cite{JQ92}, p.~571), so achieving unboundedly high entropy densities
using a stream of photons would require unboundedly high temperatures,
which we may reasonably disallow.

Further, we should remember that the limit on entropy density given by
Bekenstein's bound actually increases as information is encoded across
regions of smaller and smaller diameters.  If some technology can achieve
Bekenstein's limit, then it may change the entire form of the appropriate
scaling analysis.  However, Bekenstein's bound may not actually be
achievable, and in any case it seemingly only applies in the high-gravity
realm that we have decided to avoid.  So for now, we will stick with our
general assumption that for any particular technology, entropy density is
finite.

Table~\ref{tab:cooling} summarizes the above figures.

Now, let us examine how these different flux limits affect the maximum
possible rate of computing per unit area, under various computing
technologies.

\section{Irreversible device technologies}
\label{sec:irrtech}

Based on the switching energy issues we discussed in~\S\ref{sec:icmos}
(p.~\pageref{sec:icmos}), and typical parameters of modern VLSI fabrication
processes, we estimate that the best present-day CMOS irreversible device
technologies still generate at least $\sim 10^6$ bits of entropy per
device-switching operation.  This number will decrease somewhat over
successive VLSI technology generations, as power supply voltages and
circuit node capacitances decrease.  However, as we saw
in~\S\ref{sec:vbound} (p.~\pageref{sec:vbound}), supply voltages cannot
decrease too much because of difficulties in setting device thresholds
accurately.  Moreover, in order to cope with thermal noise, total entropy
generation per operation in irreversible CMOS circuits cannot decrease
below a reliability-dependent number of nats per operation.

One very interesting alternative semiconductor logic technology is the
``rapid single flux quantum'' (RSFQ) superconducting logic family
being developed by K.~Likharev's research group at SUNY, and
colleagues
{\cite{Likharev-92,Likharev-96,Zinoviev-98,Dorojevets-etal-99}}.  This
technology may be able to dissipate as little as 1~aJ
($10^{-18}\units{J}$) of energy per irreversible bit-operation at a
temperature of 5 K, which corresponds to an entropy generation of only
21 kilobits.

Finally, we would like to consider a ``best possible'' irreversible
technology that produces only 1 bit of physical entropy for each bit of
information that is discarded.  Merkle and Drexler (1996,
{\cite{Merkle-Drexler-96}}) argue that their proposed ``helical logic''
electronic logic technology could perform irreversible bit erasure with an
energy dissipation approaching $\kT\ln 2$, which would create just 1 bit of
entropy.  Drexler's nanomechanical ``rod logic'' is also estimated to be
capable of performing close to this limit as well (Drexler 1992
{\cite{Drexler-92}}, \S12.4.3d, p.~359).  We expect that in general, as
computational devices approach the nanoscale, a wide variety of different
device designs will be found that are capable of asymptotically approaching
the minimum entropy generation of 1 bit of entropy per bit of logical
information that is irreversibly erased.

In table~\ref{tab:irates} we combine these entropy generation figures with
the entropy flux rates from the previous section to calculate a maximum
rate of irreversible bit operations per second, per unit of enclosing
surface area, for various combinations of irreversible device technologies
and cooling technologies.  Note that these limits apply no matter how much
extra hardware one packs in along the third dimension!  As we saw
in~\S\ref{sec:rate-vs-area}, ultimately, all irreversible technologies are
limited to a fixed processing rate per unit of outer surface area, such as
the limits given here.

\begin{table}
\begin{center}
\begin{tabular}{ll|lll}
\hline\hline
&& \multicolumn{3}{c}{Operations per second per cm$^2$} \\
&& \multicolumn{3}{c}{surface in each cooling technology} \\
\cline{3-5}
Irreversible device & Entropy generated & Typical  & Fractal  & Slow atomic \\
technology          & per bit erased    & passive  & Plumbing & ballistic   \\
\hline
Modern CMOS   & $10^6$     & $\e{3.5}{16}$ & $\e{3.8}{18}$ & $10^{20}$   \\
Likharev RSFQ & $\e{2.1}{4}$ & $\e{1.7}{18}$ & $\e{1.8}{20}$ & $\e{4.8}{21}$ \\
Best possible & 1          & $\e{3.5}{22}$ & $\e{3.8}{24}$ & $10^{26}$   \\
\hline\hline
\end{tabular}
\end{center}
\caption[Maximum per-area rate for various irreversible
technologies]{Maximum rate $\ratearea$ of irreversible operations per unit
area achievable with various irreversible device technologies and cooling
technologies from table~\ref{tab:cooling}.}
\label{tab:irates}
\vspace{0.1in}
\hrule
\end{table}

Now, let us examine some reversible technologies and estimate the
scales above which they exceed these irreversible rates of performance
per unit area.

\section{Reversible technologies}

We now examine the entropy coefficients of a variety of reversible device
technologies.  Recall that the entropy coefficient of a technology
expresses the amount of entropy generated per device operation, per unit of
frequency at which the device is operated.

Based on the SCRL adiabatic circuit technology described in the previous
chapter, we calculated the entropy coefficient for typical reversible logic
gates fabricated in the fairly recent $0.5\units{\micro m}$ VLSI process
(HP14) that we used for {\FlatTop}, when operating at room temerature.  We
obtained a value of about $43\units{bits/kHz}$.  In an estimated ``best
available'' process with around $10\units{k\Ohm}$ transistor on-resistance,
1 V power supply, and 60 fF node capacitance, we estimate a somewhat lower
value of $\sim 6\units{bits/kHz}$.

SCRL's entropy coefficient might be even better in an implementation
based on low-resistance micro-electro-mechanical switches, as was
suggested by Younis (\cite{Younis-94}, \S2.7.3, p.~34).  However,
based on calculations I did using figures obtained from the MEMS
(micro-electro-mechanical systems) community, although some of the
best available MEMS switches apparently might offer an entropy
coefficient as low as $\sim 0.003\units{bits/kHz}$, the size of these
switches (on the order of 100 microns) is large enough that they do
not end up outperforming MOSFETs in terms of reversible
cost-efficiency.  In other words, although the individual switches can
run faster for a given dissipation per operation, a machine of a given
speed per unit area must be larger.

Merkle {\cite{Merkle-93a}} analyzed the energy dissipation of the
reversible transfer of a packet of 100 electrons through a minimal
quantum FET, and found it to be around $\e{3}{-21} J$ at a rate of
$1\units{GHz}$.  The corresponding entropy coefficient at room
temerature is about $1.2\units{bits/GHz}$.

Drexler's rod logic, operated reversibly, would dissipate about
$\e{2}{-21}\units{J}$ per operation at a speed of $10\units{GHz}$
(\cite{Drexler-92}, p.~354).  Its entropy coefficient at room temperature
thus comes out to $0.070\units{bits/GHz}$.

The ``parametric quantron'' superconducting reversible device of
Likharev {\cite{Likharev-82}} dissipates about $10^{-24}\units{J}$
during a 1 ns operation at around 4 K (\cite{Likharev-82} p.~322); its
entropy coefficient thus comes out at about $0.026\units{bits/GHz}$.

Finally, Merkle and Drexler's proposed helical logic
{\cite{Merkle-Drexler-96}} was analyzed by them to dissipate around
$10^{-27}\units{J}$ at 10 GHz and 1~K when operated reversibly; its entropy
coefficient thus comes out to be $10^{-5}\units{bits/GHz}$.  This is the
lowest entropy coefficient that we have encountered so far.

\begin{table}
\begin{center}
\begin{tabular}{ll}
\hline\hline
Reversible&Entropy coefficient \entco \\
device technology&in bits/GHz \\
\hline
SCRL in HP14 & $\e{4.3}{7}$ \\
SCRL in best available CMOS & $\e{6}{6}$ \\
Merkle quantum FET       & $\e{1.2}{0}$ \\
Drexler rod logic          & $\e{7.0}{-2}$ \\
Likharev parametric quantron        & $\e{2.5}{-2}$ \\
Helical logic              & $\e{1.0}{-5}$ \\
\hline\hline
\end{tabular}
\end{center}
\caption[Entropy coefficients for various reversible
technologies]{Entropy coefficients $\entco$ for some existing and proposed
asymptotically reversible logic device technologies}
\label{tab:revdev}
\vspace{0.1in}
\hrule
\end{table} 

Table~\ref{tab:revdev} summarizes the above figures.  Armed with them, we
are now in a position to calculate the scale at which the various
reversible technologies will beat the various irreversible technologies
that we mentioned in~\S\ref{sec:irrtech}.  We will measure this scale first
in terms of the number of devices required per unit area, then, in
technologies for which we know the device volume, this can be used to find
the necessary diameter or thickness of the machine.

Based on the analysis of section~\ref{sec:rate-vs-area}
(p.~\pageref{sec:rate-vs-area}), we can express the number of reversible
devices $N\tg{A}$ per unit area required to achieve a given rate
$\ratearea$ of operations per unit area as
\[
N\tg{A} = \ratearea^2 \entco / \sflux,
\]
where as usual $\entco$ is the entropy coefficient and $\sflux$ is the
entropy flux per unit area.

To achieve the same rate of operation achievable by an irreversible
machine that produces $S$ bits of entropy per operation and uses the
same cooling system, the number becomes
\[
N\tg{A} = \sflux \entco / S^2.
\]

Table~\ref{tab:nbeat} shows the number of reversible devices in various
technologies needed to beat the maximum per-area processing rate for the 3
combinations of irreversible technologies and cooling technologies that
fall along the diagonal of table~\ref{tab:irates}.  The parenthesized
numbers indicate cases in which the number of devices required may be
determined by the maximum rate of operation of the devices, rather than by
the entropy limits. The number given is the number of devices that would be
required if the individual devices could run with as high a frequency as
needed. The actual number required will most likely be higher.

\begin{table}
\begin{center}
\begin{tabular}{llll}
\hline\hline
  & \multicolumn{3}{c}{Irreversible device and cooling technology
  combination}\\
\cline{2-4}
  & best CMOS/passive 
	&    RSFQ/convective
                 & best/atomic \\
\hline
 Entropy $S$, bits/op 
   & $10^6$
       &  $\e{2.1}{4}$
            &      1 \\
 Flux $F$, $\units{bits/s\,\cm^2}$
   & $\e{3.5}{22}$
       &  $\e{3.8}{24}$
           & $10^{26}$ \\
 Rate $R$, $\units{ops/s\,\cm^2}$
   & $\e{3.5}{16}$
       &  $\e{1.8}{20}$
           & $10^{26}$ \\
\hline
 Reversible Technology
   &  \multicolumn{3}{c}{Devices required per square cm
                    to beat the above rate} \\
\hline
 SCRL/best CMOS
     & $\e{2.1}{8}$
        & $\e{5.2}{13}$
           & $\e{6}{23}$ \\
 Quantum FET
     & (42)
        & (107)
          & $\e{1.2}{17}$ \\
 Rod logic
    & (2.4)
       & $\e{6}{5}$
          & $\e{7}{15}$ \\
 Helical logic
    & $(\e{3.5}{-4})$
       & (86)
          & ($10^{12}$) \\
\hline\hline
\end{tabular}
\end{center}
\caption[Reversible device density to beat irreversible
technolgies]{Numbers $N\tg{A}$ of reversible machines per unit area
required to beat different irreversible device technologies with different
cooling strategies.  Parenthesized numbers indicate lower bounds, where the
real bounds depend on the maximum rate of operation of the devices.}
\label{tab:nbeat}
\vspace{0.1in}
\hrule
\end{table} 

To make sense of the non-parenthesized numbers in table~\ref{tab:nbeat}, we
estimate the volumes of the logic devices in various technologies. SCRL
logic gates we will take to be about
$10\units{\um}\times10\units{\um}\times1\units{\um} =
100\units{\um^3}$. Merkle's quantum FET we estimate at about
$(10\units{nm})^3$, a rod logic interlock as $40\units{nm^3}$
({\cite{Drexler-92}}, \S12.4.2, p.~357), and a helical logic switch as
$10^7\units{nm^3}$ ({\cite{Merkle-Drexler-96}}, \S5.2, p.~330).  Given
these values we produce the results in table~\ref{tab:thickness}.

\begin{table}
\begin{center}
\begin{tabular}{l|lll}
\hline\hline
                      & \multicolumn{3}{l}{Irreversible device and cooling technology combination} \\
\cline{2-4}
Reversible Technology & best CMOS/passive & RSFQ/convective & best/atomic
\\ 
\hline
SCRL/best CMOS        & 0.21 mm           & 52 m            & (4 au)      \\
Quantum FET           & (any)             & (any)           & 1.2 mm      \\
Rod logic             & (any)             & (any)           & 2.8 \um     \\
Helical logic         & (any)             & (any)           & (0.1 mm)    \\
\hline\hline
\end{tabular}
\end{center}
\caption[Thicknesses above which reversible machines win]{Thicknesses $d$ of
reversible machines that can beat different irreversible technologies in
terms of operations per unit area.  ``Any'' indicates that even a single
layer of the given reversible devices will suffice to beat the given
irreversible technology.}
\label{tab:thickness}
\vspace{0.1in}
\hrule
\end{table}

The parenthesized numbers in table~\ref{tab:thickness} need
explanation. The entries that say ``any'' indicate that even if the given
reversible devices are arranged over a surface in only a single layer, they
will still be faster than any machine built with the given irreversible
technology within that surface. As for the 0.1 mm figure we calculated for
$10^{12}$ helical logic devices per square centimeter beating the best
possible irreversible technology given a $10^{26}\units{bit/cm^2}$ entropy
flux, it is probably inaccurate because the individual helical logic
devices probably couldn't be made to run at the implied rate of 100 THz.

The entry in the upper right corner of the table indicates that a machine
built with current CMOS reversible technology, such as SCRL, would have to
be the size of the inner solar system (!!) before it would be faster per
unit area than the most efficient possible irreversible
technology. Needless to say, a machine this large, composed mostly of solid
silicon, would collapse under its own gravity.

In any case, the table indicates overall that most of the listed reversible
technologies outperform most irreversible technologies, in terms of raw
numbers of operations per second per unit area, for a wide range of cooling
capabilities and for machines at a reasonable scale. Current CMOS
reversible technology does not perform so well against the most efficient
conceivable irreversible technologies, but it can still beat machines based
on contemporary irreversible CMOS technology at reasonable scales.

One caveat to the above results is that in general a reversible device
operation is not quite as computationally useful as an irreversible
operation, due to the algorithmic issues we discussed in
{\S\ref{sec:revthy}}. However, for problems that have efficient reversible
algorithms, like physical simulations (see \S{\ref{sec:physsim}}), a small
constant number of reversible device operations should suffice to do as
much useful computational work as a single irreversible operation. The
diameters in table~\ref{tab:thickness} should therefore be increased by a
factor of the same small constant.

\section{Future device technologies---Conclusion}

In this chapter, we listed a number of existing and proposed device
technologies for both irreversible and reversible logic, and a variety of
existing and hypothetical cooling technologies.  Many of the technologies
described cannot currently be built, but it is plausible that someday they
might, and in any case all the technologies described serve as interesting
points for comparison.

For each device technology, we gave the explicit numerical parameters
determining its entropy generation, and from this, we determined limiting
rates of operation per unit area for the irreversible technologies.  Then,
based on the superior scaling laws we have derived for time-proportionately
reversible machines, we estimated the thickness of the reversible machines
that would beat the irreversible machines' performance per unit area.

The upshot is that although present reversible technology is not so great,
many of the proposed future reversible technologies would outperform
{\emph{any}} irreversible technology in terms of rate per unit area, even
when considering only very thin layers---on the order of microns to
millimeters thick---of packed logic devices in the given technology.  This
result holds firm unless a way is found to remove entropy from a system at
a flux much higher than our rather arbitrarily-chosen maximum rate of
$10^{26}$ bits per square centimeter per second.  (A rate corresponding to
1 bit per cubic {\AA}ngstrom, moving at an arbitrary 1 m/s.)

These figures argue that in the long term, as computing technology moves
down into the nanometer realm, and (eventually) away from conventional
bulk-sem\-i\-con\-duc\-tor techniques, reversibility will become a clear
win in any macroscopic-scale computers built from such nano-scale devices.

This long-term trend makes it interesting and important to study reversible
computer architectures and algorithms even today, because no matter the
precise details of the future nano-scale device technologies that might
become dominant, we can expect that using them in an asymptotically
reversible way will confer substantially more computational power, in many
applications for all but the smallest-scale machines.  We will need
reversible architectures and algorithms eventually; we can get a head start
by designing them today.  In the next chapter, we describe what we have
learned along that direction so far.

% End chapter.
\cleardoublepage