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% ft.tex - Flattop processor schematics and layout
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\chapter{FlatTop processor schematics and layouts}
\markboth{APPENDIX \thechapter. FLATTOP SCHEMATICS AND LAYOUT}
         {APPENDIX \thechapter. FLATTOP SCHEMATICS AND LAYOUT}
\label{ch:ft}

\def\draftid{$\ $Id: ft.tex,v 1.1.2.2.2.3 1999/05/13 19:19:09 mpf Exp $\ $}

This appendix gives the detailed Cadence schematics and layout for the
{\FlatTop} universal parallel reversible processor which we discussed
in~\S\ref{sec:scrlexp}.  These diagrams were also included in our
conference paper {\cite{Frank-etal-98a}}.

{\ed{Should I include more schematics?  More layouts?  More up-to-date
versions of everything?}}

\section{High-level blocks}

Figure \ref{fig:pe} shows a schematic block diagram of a single processing
element cell.  Note the three blocks, one for each of the three stages in
the 3-phase SCRL pipeline which makes up the logic of the cell.  The
lollipop-shaped icon above each stage represents the set of swinging supply
rails, in a particular phase, which drive the stage adiabatically.  The
cell has four inputs A, B, C, D which come from the four neighboring cells,
and four corresponding outputs which go back out to those cells.

The SHIFT in and out signals are global signals shared by all cells; they
tell the cells whether to operate in initialization mode or normal mode.
In initialization mode the array of cells behaves as a shift register, and
the array contents may be shifted in and out; in normal mode, the array
just obeys the BBMCA update rules.

The boxes attached to the input are for setting initial conditions during
HSPICE simulation of the circuit.

\begin{figure}
\centerline{\psfig{width=\textwidth,file=pe.eps}}
\caption[Block diagram of PE cell]{Cadence schematic block diagram of the
{\FlatTop} PE cell.  The three blocks are the 3 SCRL logic stages, each
clocked by a separate set of clock rails, indicated by the ``lollipop''
icons above the blocks, whose phases are offset by 1/3 cycle from each
other.}
\label{fig:pe}
\vspace{.1in}\hrule
\end{figure}

Figure \ref{fig:icon} shows our schematic icon representing an entire
processing element.  The icon portrays the 2$\times$2 block of BBMCA cells
which the PE is updating, with the PE inputs and outputs placed in the
appropriate cells.  The cell grid is rotated 45 degrees from the
representation in fig.~\ref{fig:pegrid} to show how the CA array is
orientated with respect to the edges of the chip.  With this orientation,
the array of processing elements can communicate along pathways that run
parallel to the chip edges, making layout easier.

\begin{figure}
\centerline{\psfig{width=2in,file=icon.eps}}
\caption[Icon for a single {\FlatTop} cell]{Icon for a single {\FlatTop}
cell.  The depiction graphically illustrates the block of 4 CA cells,
oriented by 45$^\circ$ to the inter-PE wiring, that is updated by the PE.
The two terminals in each cell connect to and from the neighboring PE in
the given direction, whose icon is overlapped with this one, as a reminder
that the two PEs take turns updating the same CA cell.}
\label{fig:icon}
\vspace{.1in}\hrule
\end{figure}

Figure \ref{fig:corner} shows one corner of an array of these processing
elements.  In the upper left corners are pathways used for initialization
and reading out the whole array when used as a shift-register.  Along the
edges of the array are edge cells which provide connections to pins,
allowing the chip to communicate with other chips during normal operation.
There are not enough pins to allow communication everywhere along the edge,
so in other places the wires at the edge just loop around to feed back into
the array.  Every PE receives the global shift signals, which run
horizontally.

\begin{figure}
\centerline{\psfig{width=\textwidth,file=corner.eps}}
\caption[One corner of an array of {\FlatTop} PEs]{Schematic diagram of the
upper-left corner of a large array of {\FlatTop} processing elements.  The
rows and columns of cells of CA array being simulating can be seen running
diagonally across the array.  You can see how the PE icons
(fig.~\ref{fig:icon}) are overlapped to represent the shared management of
each CA cell.  Meanwhile, clock-power signals are strapped horizontally
across the array.  Periodically along the edge of the array are units for
inter-chip communication.  Other signals along the edges are simply wrapped
around to a neighboring edge cell.  The buffers in the far upper left
corner provide initialization and readout capabilities.}
\label{fig:corner}
\vspace{.1in}\hrule
\end{figure}

Figure \ref{fig:array} shows the entire 20$\times$20 array of processing
elements which we fabricated for testing purposes.

\begin{figure}
\centerline{\psfig{width=\textwidth,file=array.eps}}
\caption[The full 20$\times$20 array of PEs]{Schematic block diagram of the
full 20$\times$20 array of {\FlatTop} processing elements which we
fabricated on each die.  This simply extends the structure shown in
fig.~\ref{fig:corner}.}
\label{fig:array}
\vspace{.1in}\hrule
\end{figure}

\section{Detailed gate schematics}

Below are the schematics for the logic in the three stages of each cell.
We have not yet had time to size the transistors in our design so as to
minimize power, but within each gate, we have, for uniformity, sized its
transistors so that the worst-case conductances are the same as that of an
inverter with a minimum-width {\nFET} and a twice-minimum-width {\pFET}.

Figure \ref{fig:stage1} shows the logic in stage 1 which computes the
inverses of the inputs, together with the inverse of the S (static) signal
used in stage 2.  Note that S is turned on when in $sh$ (shift) mode.  This
special case was added to support array initialization.

\begin{figure}
\centerline{\psfig{width=\textwidth,file=stage1.eps}}
\caption[Stage 1 logic gate]{Stage 1 logic, $\overline{S}=\overline{sh + (A+C)(B+D)}$.}
\label{fig:stage1}
\vspace{.1in}\hrule
\end{figure}

Figure \ref{fig:arbiter}(a) shows the gate used for computing each
second-stage output.  The forward part of stage 2 includes four repititions
of this gate, differing as to which inputs are fed to the $A,B,C,D$ pins,
plus 6 ``fast'' inverters for generating the $A,B,C,D,S,shift$ signals from
their inverses using the $f\phi_2$ and $\overline{f\phi_2}$ rails, plus
one other inverter for generating $\overline{S}$ on the stage 2 output.

\begin{figure}
\centerline{(a)\psfig{width=0.6\textwidth,rwidth=0.4\textwidth,file=arbiter.eps}(b)\psfig{width=0.6\textwidth,rwidth=0.4\textwidth,file=swapper.eps}}
\caption[Logic for stages 2 and 3]{(a) Gate for computing $\overline{A_{out}}$ in stage 2. (b) Gate for computing
$A'=\overline{\overline{sh}\ \overline{A} + sh\ \overline{C}}$ in stage 3.}
\label{fig:arbiter}
\vspace{.1in}\hrule
\end{figure}

Finally, figure \ref{fig:arbiter}(b) shows the gate that is repeated four times
(with different pin assignments) in the forwards part of stage 3.  This
gate selects either $A$ or the bit in the opposite corner of the block for
passing through to the output, depending on $sh$.  Thus if $sh$ is on,
input bits go to the opposite output bits, enabling the array as a whole to
act as one large shift register, which can be used to initialize the array
contents.

\section{Cell layout}

Figure \ref{fig:celllayout} shows the complete layout of a single PE cell.
For clarity, the metal3 rails that run vertically across the entire cell
are not shown.  The cell measures 167.6 $\mu$m $\times$ 91.3 $\mu$m.

\begin{figure}
\centerline{\psfig{width=\textwidth,file=celllayout.eps}}
\caption[Complete layout of a single {\FlatTop} PE]{Complete layout of a
single {\FlatTop} PE cell, except for metal3 layer.}
\label{fig:celllayout}
\vspace{.1in}\hrule
\end{figure}

{\ed{Should I also include layouts of individual gates?  None of our papers
had that.  But since theses can be infinitely long, I could include them
here.  If I do include them, make sure I use mine and not Carlin's!  Or at
least say whose they are.}}

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